IEEE Std 1364-1995 IEEE Standard Hardware Description Language Based on the Verilog® Hardware Description Language -Description

Abstract: The Verilog® Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.

Keywords: computer, computer languages, electronic systems, digital systems, hardware, hardware design, hardware description languages, HDL, programming language interface, PLI, Verilog HDL, Verilog PLI, Verilog®

Content

• 1. Overview
• • 1.1 Objectives of this standard
  • 1.2 Conventions used in this standard
  • 1.3 Syntactic description
  • 1.4 Contents of this standard
  • 1.5 Header file listings
  • 1.6 Examples
  • 1.7 Prerequisites
• 2. Lexical conventions
• • 2.1 Lexical tokens
  • 2.2 White space
  • 2.3 Comments
  • 2.4 Operators
  • 2.5 Numbers
  • • 2.5.1 Integer constants
    • 2.5.2 Real constants
    • 2.5.3 Conversion
  • 2.6 Strings
  • • 2.6.1 String variable declaration
    • 2.6.2 String manipulation
    • 2.6.3 Special characters in strings
  • 2.7 Identifiers, keywords, and system names
  • • 2.7.1 Escaped identifiers
    • 2.7.2 Keywords
    • 2.7.3 System tasks and functions
    • 2.7.4 Compiler directives
• 3. Data types
• • 3.1 Value set
  • 3.2 Nets and registers
  • • 3.2.1 Nets
    • 3.2.2 Registers
  • 3.3 Vectors
  • • 3.3.1 Specifying vectors
    • 3.3.2 Vector net accessibility
  • 3.4 Strengths
  • • 3.4.1 Charge strength
    • 3.4.2 Drive strength
  • 3.5 Implicit declarations
  • 3.6 Net initialization
  • 3.7 Net types
  • • 3.7.1 Wire and tri nets
    • 3.7.2 Wired nets
    • 3.7.3 Trireg net
    • 3.7.4 Tri0 and tri1 nets
    • 3.7.5 Supply nets
  • 3.8 Memories
  • 3.9 Integers, reals, times, and realtimes
  • • 3.9.1 Operators and real numbers
    • 3.9.2 Conversion
  • 3.10 Parameters
  • 3.11 Name spaces
• 4. Expressions
• • 4.1 Operators
  • • 4.1.1 Operators with real operands
    • 4.1.2 Binary operator precedence
    • 4.1.3 Using integer numbers in expressions
    • 4.1.4 Expression evaluation order
    • 4.1.5 Arithmetic operators
    • 4.1.6 Arithmetic expressions with registers and integers
    • 4.1.7 Relational operators
    • 4.1.8 Equality operators
    • 4.1.9 Logical operators
    • 4.1.10 Bit-wise operators
    • 4.1.11 Reduction operators
    • 4.1.12 Shift operators
    • 4.1.13 Conditional operator
    • 4.1.14 Concatenations
    • 4.1.15 Event or
  • 4.2 Operands
  • • 4.2.1 Net and register bit-select and part-select addressing
    • 4.2.2 Memory addressing
    • 4.2.3 Strings
  • 4.3 Minimum, typical, and maximum delay expressions
  • 4.4 Expression bit lengths
  • • 4.4.1 Rules for expression bit lengths
    • 4.4.2 An example of an expression bit-length problem
• 5. Scheduling semantics
• • 5.1 Execution of a model
  • 5.2 Event simulation
  • 5.3 The stratified event queue
  • 5.4 The Verilog simulation reference model
  • • 5.4.1 Determinism
    • 5.4.2 Nondeterminism
  • 5.5 Race conditions
  • 5.6 Scheduling implication of assignments
  • • 5.6.1 Continuous assignment
    • 5.6.2 Procedural continuous assignment
    • 5.6.3 Blocking assignment
    • 5.6.4 Nonblocking assignment
    • 5.6.5 Switch (transistor) processing
    • 5.6.6 Port connections
    • 5.6.7 Functions and tasks
• 6. Assignments
• • 6.1 Continuous assignments
  • • 6.1.1 The net declaration assignment
    • 6.1.2 The continuous assignment statement
    • 6.1.3 Delays
    • 6.1.4 Strength
  • 6.2 Procedural assignments
• 7. Gate and switch level modeling
• • 7.1 Gate and switch declaration syntax
  • • 7.1.1 The gate type specification
    • 7.1.2 The drive strength specification
    • 7.1.3 The delay specification
    • 7.1.4 The primitive instance identifier
    • 7.1.5 The range specification
    • 7.1.6 Primitive instance connection list
  • 7.2 And, nand, nor, or, xor, and xnor, gates
  • 7.3 Buf and not gates
  • 7.4 Bufif1, bufif0, notif1, and notif0 gates
  • 7.5 MOS switches
  • 7.6 Bidirectional pass switches
  • 7.7 CMOS switches
  • 7.8 Pullup and pulldown sources
  • 7.9 Implicit net declarations
  • 7.10 Logic strength modeling
  • 7.11 Strengths and values of combined signals
  • • 7.11.1 Combined signals of unambiguous strength
    • 7.11.2 Ambiguous strengths: sources and combinations
    • 7.11.3 Ambiguous strength signals and unambiguous signals
    • 7.11.4 Wired logic net types
  • 7.12 Strength reduction by nonresistive devices
  • 7.13 Strength reduction by resistive devices
  • 7.14 Strengths of net types
  • • 7.14.1 Tri0 and tri1 net strengths
    • 7.14.2 Trireg strength
    • 7.14.3 Supply0 and supply1 net strengths
  • 7.15 Gate and net delays
  • • 7.15.1 Min:typ:max delays
    • 7.15.2 Trireg net charge decay
• 8. User-defined primitives (UDPs)
• • 8.1 UDP definition
  • • 8.1.1 UDP header
    • 8.1.2 UDP port declarations
    • 8.1.3 Sequential UDP initial statement
    • 8.1.4 UDP state table
    • 8.1.5 Z values in UDP
    • 8.1.6 Summary of symbols
  • 8.2 Combinational UDPs
  • 8.3 Level-sensitive sequential UDPs
  • 8.4 Edge-sensitive sequential UDPs
  • 8.5 Sequential UDP initialization
  • 8.6 UDP instances
  • 8.7 Mixing level-sensitive and edge-sensitive descriptions
  • 8.8 Level-sensitive dominance
• 9. Behavioral modeling
• • 9.1 Behavioral model overview
  • 9.2 Procedural assignments
  • • 9.2.1 Blocking procedural assignments
    • 9.2.2 The nonblocking procedural assignment
  • 9.3 Procedural continuous assignments
  • • 9.3.1 The assign and deassign procedural statements
    • 9.3.2 The force and release procedural statements
  • 9.4 Conditional statement
  • • 9.4.1 If-else-if construct
  • 9.5 Case statement
  • • 9.5.1 Case statement with don"t-cares
    • 9.5.2 Constant expression in case statement
  • 9.6 Looping statements
  • 9.7 Procedural timing controls
  • • 9.7.1 Delay control
    • 9.7.2 Event control
    • 9.7.3 Named events
    • 9.7.4 Event or operator
    • 9.7.5 Level-sensitive event control
    • 9.7.6 Intra-assignment timing controls
  • 9.8 Block statements
  • • 9.8.1 Sequential blocks
    • 9.8.2 Parallel blocks
    • 9.8.3 Block names
    • 9.8.4 Start and finish times
  • 9.9 Structured procedures
  • • 9.9.1 Initial construct
    • 9.9.2 Always construct
• 10. Tasks and functions
• • 10.1 Distinctions between tasks and functions
  • 10.2 Tasks and task enabling
  • • 10.2.1 Defining a task
    • 10.2.2 Task enabling and argument passing
    • 10.2.3 Task memory usage and concurrent activation
  • 10.3 Functions and function calling
  • • 10.3.1 Defining a function
    • 10.3.2 Returning a value from a function
    • 10.3.3 Calling a function
    • 10.3.4 Function rules
• 11. Disabling of named blocks and tasks
• 12. Hierarchical structures
• • 12.1 Modules
  • • 12.1.1 Top-level modules
    • 12.1.2 Module instantiation
  • 12.2 Overriding module parameter values
  • • 12.2.1 Defparam statement
    • 12.2.2 Module instance parameter value assignment
    • 12.2.3 Parameter dependence
  • 12.3 Ports
  • • 12.3.1 Port definition
    • 12.3.2 Port declarations
    • 12.3.3 Connecting module ports by ordered list
    • 12.3.4 Connecting module ports by name
    • 12.3.5 Real numbers in port connections
    • 12.3.6 Connecting dissimilar ports
    • 12.3.7 Port connection rules
    • 12.3.8 Net types resulting from dissimilar port connections
  • 12.4 Hierarchical names
  • • 12.4.1 Upwards name referencing
  • 12.5 Scope rules
• 13. Specify blocks
• • 13.1 Specify block declaration
  • 13.2 Declaring parameters in specify blocks
  • 13.3 Module path declarations
  • • 13.3.1 Module path restrictions
    • 13.3.2 Simple module paths
    • 13.3.3 Edge-sensitive paths
    • 13.3.4 State-dependent paths
    • 13.3.5 Full connection and parallel connection paths
    • 13.3.6 Declaring multiple module paths in a single statement
    • 13.3.7 Module path polarity
  • 13.4 Assigning delays to module paths
  • • 13.4.1 Specifying transition delays on module paths
    • 13.4.2 Specifying x transition delays
  • 13.5 Mixing module path delays and distributed delays
  • 13.6 Driving wired logic
  • 13.7 Controlling pulses on module paths with PATHPULSE$
• 14. System tasks and functions
• • 14.1 Display system tasks
  • • 14.1.1 The display and write tasks
    • 14.1.2 Strobed monitoring
    • 14.1.3 Continuous monitoring
  • 14.2 File input-output system tasks
  • • 14.2.1 Opening and closing files
    • 14.2.2 File output system tasks
    • 14.2.3 Loading memory data from a file
  • 14.3 Timescale system tasks
  • • 14.3.1 $printtimescale
    • 14.3.2 $timeformat
  • 14.4 Simulation control system tasks
  • • 14.4.1 $finish
    • 14.4.2 $stop
  • 14.5 Timing check system tasks
  • • 14.5.1 $setup
    • 14.5.2 $hold
    • 14.5.3 $setuphold
    • 14.5.4 $width
    • 14.5.5 $period
    • 14.5.6 $skew
    • 14.5.7 $recovery
    • 14.5.8 $nochange
    • 14.5.9 Edge-control specifiers
    • 14.5.10 Notifiers: user-defined responses to timing violations
    • 14.5.11 Enabling timing checks with conditioned events
  • 14.6 PLA modeling system tasks
  • • 14.6.1 Array types
    • 14.6.2 Array logic types
    • 14.6.3 Logic array personality declaration and loading
    • 14.6.4 Logic array personality formats
  • 14.7 Stochastic analysis tasks
  • • 14.7.1 $q_initialize
    • 14.7.2 $q_add
    • 14.7.3 $q_remove
    • 14.7.4 $q_full
    • 14.7.5 $q_exam
    • 14.7.6 Status codes
  • 14.8 Simulation time system functions
  • • 14.8.1 $time
    • 14.8.2 $stime
    • 14.8.3 $realtime
  • 14.9 Conversion functions for reals
  • 14.10 Probabilistic distribution functions
  • • 14.10.1 $random function
    • 14.10.2 $dist_functions
• 15. Value change dump (VCD) file
• • 15.1 Creating the value change dump file
  • • 15.1.1 Specifying the name of the dump file ($dump file)
    • 15.1.2 Specifying the variables to be dumped ($dumpvars)
    • 15.1.3 Stopping and resuming the dump ($dumpoff/$dumpon)
    • 15.1.4 Generating a checkpoint ($dumpall)
    • 15.1.5 Limiting the size of the dump file ($dumplimit)
    • 15.1.6 Reading the dump file during simulation ($dumpflush)
  • 15.2 Format of the VCD file
  • • 15.2.1 Syntax of the VCD file
    • 15.2.2 Formats of variable values
    • 15.2.3 Description of keyword commands
    • 15.2.4 VCD file format example
• 16. Compiler directives
• • 16.1 Ĭcelldefine and Ĭendcelldefine
  • 16.2 Ĭdefault_nettype
  • 16.3 Ĭdefine and Ĭundef
  • • 16.3.1 Ĭdefine
    • 16.3.2 Ĭundef
  • 16.4 Ĭifdef, Ĭelse, Ĭendif
  • 16.5 Ĭinclude
  • 16.6 Ĭresetall
  • 16.7 Ĭtimescale
  • 16.8 Ĭunconnected_drive and Ĭnounconnected_drive
• 17. PLI TF and ACC interface mechanism
• • 17.1 PLI purpose and history
  • 17.2 User-defined task or function names
  • 17.3 Overloading built-in system task and function names
  • 17.4 User-supplied PLI applications
  • • 17.4.1 The calltf class of PLI applications
    • 17.4.2 The checktf class of PLI applications
    • 17.4.3 The sizetf class of PLI applications
    • 17.4.4 The misctf class of PLI applications
    • 17.4.5 The consumer class of PLI applications
  • 17.5 Associating PLI applications to a class and system task/function name
  • 17.6 PLI application arguments
  • • 17.6.1 The data C argument
    • 17.6.2 The reason C argument
    • 17.6.3 The paramvc C argument
  • 17.7 User-defined system task and function arguments
  • 17.8 PLI include files for TF and ACC routines
• 18. Using ACC routines
• • 18.1 ACC routine definition
  • 18.2 The handle data type
  • 18.3 Using ACC routines
  • • 18.3.1 Header files
    • 18.3.2 Initializing ACC routines
    • 18.3.3 Setting the development version
    • 18.3.4 Exiting ACC routines
  • 18.4 List of ACC routines by major category
  • • 18.4.1 Fetch routines
    • 18.4.2 Handle routines
    • 18.4.3 Next routines
    • 18.4.4 Modify routines
    • 18.4.5 Miscellaneous routines
    • 18.4.6 VCL routines
  • 18.5 Accessible objects
  • • 18.5.1 ACC routines that operate on module instances
    • 18.5.2 ACC routines that operate on module ports
    • 18.5.3 ACC routines that operate on bits of a port
    • 18.5.4 ACC routines that operate on module paths or data paths
    • 18.5.5 ACC routines that operate on intermodule paths
    • 18.5.6 ACC routines that operate on top-level modules
    • 18.5.7 ACC routines that operate on primitive instances
    • 18.5.8 ACC routines that operate on primitive terminals
    • 18.5.9 ACC routines that operate on nets
    • 18.5.10 ACC routines that operate on registers
    • 18.5.11 ACC routines that operate on integer, real, and time variables
    • 18.5.12 ACC routines that operate on named events
    • 18.5.13 ACC routines that operate on parameters and specparams
    • 18.5.14 ACC routines that operate on timing checks
    • 18.5.15 ACC routines that operate on timing check terminals
    • 18.5.16 ACC routines that operate on user-defined system task/function arguments
  • 18.6 ACC routine types and fulltypes
  • 18.7 Error handling
  • • 18.7.1 Suppressing error messages
    • 18.7.2 Enabling warnings
    • 18.7.3 Testing for errors
    • 18.7.4 Example
    • 18.7.5 Exception values
  • 18.8 Reading and writing delay values
  • • 18.8.1 Number of delays for Verilog HDL objects
    • 18.8.2 ACC routine configuration
    • 18.8.3 Determining the number of arguments for ACC delay routines
  • 18.9 String handling
  • • 18.9.1 ACC routines share an internal string buffer
    • 18.9.2 String buffer reset
    • 18.9.3 Preserving string values
    • 18.9.4 Example of preserving string values
  • 18.10 Using VCL ACC routines
  • • 18.10.1 VCL objects
    • 18.10.2 The VCL record definition
    • 18.10.3 Affects of acc_initialize() and acc_close() on VCL consumer routines
    • 18.10.4 An example of using VCL ACC routines
• 19. ACC routine definitions
• • 19.1 acc_append_delays()
  • 19.2 acc_append_pulsere()
  • 19.3 acc_close()
  • 19.4 acc_collect()
  • 19.5 acc_compare_handles()
  • 19.6 acc_configure()
  • 19.7 acc_count()
  • 19.8 acc_fetch_argc()
  • 19.9 acc_fetch_argv()
  • 19.10 acc_fetch_attribute()
  • 19.11 acc_fetch_attribute_int()
  • 19.12 acc_fetch_attribute_str()
  • 19.13 acc_fetch_defname()
  • 19.14 acc_fetch_delay_mode()
  • 19.15 acc_fetch_delays()
  • 19.16 acc_fetch_direction()
  • 19.17 acc_fetch_edge()
  • 19.18 acc_fetch_fullname()
  • 19.19 acc_fetch_fulltype()
  • 19.20 acc_fetch_index()
  • 19.21 acc_fetch_location()
  • 19.22 acc_fetch_name()
  • 19.23 acc_fetch_paramtype()
  • 19.24 acc_fetch_paramval()
  • 19.25 acc_fetch_polarity()
  • 19.26 acc_fetch_precision()
  • 19.27 acc_fetch_pulsere()
  • 19.28 acc_fetch_range()
  • 19.29 acc_fetch_size()
  • 19.30 acc_fetch_tfarg(), acc_fetch_itfarg()
  • 19.31 acc_fetch_tfarg_int(), acc_fetch_itfarg_int()
  • 19.32 acc_fetch_tfarg_str(), acc_fetch_itfarg_str()
  • 19.33 acc_fetch_timescale_info()
  • 19.34 acc_fetch_type()
  • 19.35 acc_fetch_type_str()
  • 19.36 acc_fetch_value()
  • 19.37 acc_free()
  • 19.38 acc_handle_by_name()
  • 19.39 acc_handle_calling_mod_m()
  • 19.40 acc_handle_condition()
  • 19.41 acc_handle_conn()
  • 19.42 acc_handle_datapath()
  • 19.43 acc_handle_hiconn()
  • 19.44 acc_handle_interactive_scope()
  • 19.45 acc_handle_loconn()
  • 19.46 acc_handle_modpath()
  • 19.47 acc_handle_notifier()
  • 19.48 acc_handle_object()
  • 19.49 acc_handle_parent()
  • 19.50 acc_handle_path()
  • 19.51 acc_handle_pathin()
  • 19.52 acc_handle_pathout()
  • 19.53 acc_handle_port()
  • 19.54 acc_handle_scope()
  • 19.55 acc_handle_simulated_net()
  • 19.56 acc_handle_tchk()
  • 19.57 acc_handle_tchkarg1()
  • 19.58 acc_handle_tchkarg2()
  • 19.59 acc_handle_terminal()
  • 19.60 acc_handle_tfarg(), acc_handle_itfarg()
  • 19.61 acc_handle_tfinst()
  • 19.62 acc_initialize()
  • 19.63 acc_next()
  • 19.64 acc_next_bit()
  • 19.65 acc_next_cell()
  • 19.66 acc_next_cell_load()
  • 19.67 acc_next_child()
  • 19.68 acc_next_driver()
  • 19.69 acc_next_hiconn()
  • 19.70 acc_next_input()
  • 19.71 acc_next_load()
  • 19.72 acc_next_loconn()
  • 19.73 acc_next_modpath()
  • 19.74 acc_next_net()
  • 19.75 acc_next_output()
  • 19.76 acc_next_parameter()
  • 19.77 acc_next_port()
  • 19.78 acc_next_portout()
  • 19.79 acc_next_primitive()
  • 19.80 acc_next_scope()
  • 19.81 acc_next_specparam()
  • 19.82 acc_next_tchk()
  • 19.83 acc_next_terminal()
  • 19.84 acc_next_topmod()
  • 19.85 acc_object_in_typelist()
  • 19.86 acc_object_of_type()
  • 19.87 acc_product_type()
  • 19.88 acc_product_version()
  • 19.89 acc_release_object()
  • 19.90 acc_replace_delays()
  • 19.91 acc_replace_pulsere()
  • 19.92 acc_reset_buffer()
  • 19.93 acc_set_interactive_scope()
  • 19.94 acc_set_pulsere()
  • 19.95 acc_set_scope()
  • 19.96 acc_set_value()
  • 19.97 acc_vcl_add()
  • 19.98 acc_vcl_delete()
  • 19.99 acc_version()
• 20. Using TF routines
• • 20.1 TF routine definition
  • 20.2 TF routine parameters
  • 20.3 Reading and writing parameter values
  • • 20.3.1 Reading and writing 2-state parameter values
    • 20.3.2 Reading and writing 4-state values
    • 20.3.3 Reading and writing strength values
    • 20.3.4 Reading and writing to memories
    • 20.3.5 Reading and writing string values
    • 20.3.6 Writing return values of user-defined functions
    • 20.3.7 Writing the correct C data types
  • 20.4 Value change detection
  • 20.5 Simulation time
  • 20.6 Simulation synchronization
  • 20.7 Instances of user-defined task or functions
  • 20.8 Module and scope instance names
  • 20.9 Saving information from one system TF call to the next
  • 20.10 Displaying output messages
  • 20.11 Stopping and finishing
• 21. TF routine definitions
• • 21.1 io_mcdprintf()
  • 21.2 io_printf()
  • 21.3 mc_scan_plusargs()
  • 21.4 tf_add_long()
  • 21.5 tf_asynchoff(), tf_iasynchoff()
  • 21.6 tf_asynchon(), tf_iasynchon()
  • 21.7 tf_clearalldelays(), tf_iclearalldelays()
  • 21.8 tf_compare_long()
  • 21.9 tf_copypvc_flag(), tf_icopypvc_flag()
  • 21.10 tf_divide_long()
  • 21.11 tf_dofinish()
  • 21.12 tf_dostop()
  • 21.13 tf_error()
  • 21.14 tf_evaluatep(), tf_ievaluatep()
  • 21.15 tf_exprinfo(), tf_iexprinfo()
  • 21.16 tf_getcstringp(), tf_igetcstringp()
  • 21.17 tf_getinstance()
  • 21.18 tf_getlongp(), tf_igetlongp()
  • 21.19 tf_getlongtime(), tf_igetlongtime()
  • 21.20 tf_getnextlongtime()
  • 21.21 ()tf_getp(), tf_igetp
  • 21.22 tf_getpchange(), tf_igetpchange()
  • 21.23 tf_getrealp(), tf_igetrealp()
  • 21.24 tf_getrealtime(), tf_igetrealtime()
  • 21.25 tf_gettime(), tf_igettime()
  • 21.26 tf_gettimeprecision(), tf_igettimeprecision()
  • 21.27 tf_gettimeunit(), tf_igettimeunit()
  • 21.28 tf_getworkarea(), tf_igetworkarea()
  • 21.29 tf_long_to_real()
  • 21.30 tf_longtime_tostr()
  • 21.31 tf_message()
  • 21.32 tf_mipname(), tf_imipname()
  • 21.33 tf_movepvc_flag(), tf_imovepvc_flag()
  • 21.34 tf_multiply_long()
  • 21.35 tf_nodeinfo(), tf_inodeinfo()
  • 21.36 tf_nump(), tf_inump()
  • 21.37 tf_propagatep(), tf_ipropagatep()
  • 21.38 tf_putlongp(), tf_iputlongp()
  • 21.39 tf_putp(), tf_iputp()
  • 21.40 tf_putrealp(), tf_iputrealp()
  • 21.41 tf_read_restart()
  • 21.42 tf_real_to_long()
  • 21.43 tf_rosynchronize(), tf_irosynchronize()
  • 21.44 tf_scale_longdelay()
  • 21.45 tf_scale_realdelay()
  • 21.46 tf_setdelay(), tf_isetdelay()
  • 21.47 tf_setlongdelay(), tf_isetlongdelay()
  • 21.48 tf_setrealdelay(), tf_isetrealdelay()
  • 21.49 tf_setworkarea(), tf_isetworkarea()
  • 21.50 tf_sizep(), tf_isizep()
  • 21.51 tf_spname(), tf_ispname()
  • 21.52 tf_strdelputp(), tf_istrdelputp()
  • 21.53 tf_strgetp(), tf_istrgetp()
  • 21.54 tf_strgettime()
  • 21.55 tf_strlongdelputp(), tf_istrlongdelputp()
  • 21.56 tf_strrealdelputp(), tf_istrrealdelputp()
  • 21.57 tf_subtract_long()
  • 21.58 tf_synchronize(), tf_isynchronize()
  • 21.59 tf_testpvc_flag(), tf_itestpvc_flag()
  • 21.60 tf_text()
  • 21.61 tf_typep(), tf_itypep()
  • 21.62 tf_unscale_longdelay()
  • 21.63 tf_unscale_realdelay()
  • 21.64 tf_warning()
  • 21.65 tf_write_save()
• 22. Using VPI routines
• • 22.1 The VPI interface
  • • 22.1.1 VPI callbacks
    • 22.1.2 VPI access to Verilog HDL objects and simulation objects
    • 22.1.3 Error handling
  • 22.2 VPI object classifications
  • • 22.2.1 Accessing object relationships and properties
    • 22.2.2 Delays and values
  • 22.3 List of VPI routines by functional category
  • 22.4 Key to object model diagrams
  • • 22.4.1 Diagram key for objects and classes
    • 22.4.2 Diagram key for accessing properties
    • 22.4.3 Diagram key for traversing relationships
  • 22.5 Object data model diagrams
  • • 22.5.1 Module
    • 22.5.2 Scope, task, function, IO declaration
    • 22.5.3 Ports
    • 22.5.4 Nets
    • 22.5.5 Regs
    • 22.5.6 Variables, named event
    • 22.5.7 Memory
    • 22.5.8 Parameter, specparam
    • 22.5.9 Primitive, prim term
    • 22.5.10 UDP
    • 22.5.11 Module path, timing check, intermodule path
    • 22.5.12 Task and function call
    • 22.5.13 Continuous assignment
    • 22.5.14 Simple expressions
    • 22.5.15 Expressions
    • 22.5.16 Process, block, statement, event statement
    • 22.5.17 Assignment, delay control, event control, repeat control
    • 22.5.18 While, repeat, wait, for, forever
    • 22.5.19 If, if-else, case
    • 22.5.20 Assign statement, deassign, force, release, disable
    • 22.5.21 Callback, time queue
• 23. VPI routine definitions
• • 23.1 vpi_chk_error()
  • 23.2 vpi_compare_objects()
  • 23.3 vpi_free_object()
  • 23.4 vpi_get()
  • 23.5 vpi_get_cb_info()
  • 23.6 vpi_get_delays()
  • 23.7 vpi_get_str()
  • 23.8 vpi_get_systf_info()
  • 23.9 vpi_get_time()
  • 23.10 vpi_get_value()
  • 23.11 vpi_get_vlog_info()
  • 23.12 vpi_handle()
  • 23.13 vpi_handle_by_index()
  • 23.14 vpi_handle_by_name()
  • 23.15 vpi_handle_multi()
  • 23.16 vpi_iterate()
  • 23.17 vpi_mcd_close()
  • 23.18 vpi_mcd_name()
  • 23.19 vpi_mcd_open()
  • 23.20 vpi_mcd_printf()
  • 23.21 vpi_printf()
  • 23.22 vpi_put_delays()
  • 23.23 vpi_put_value()
  • 23.24 vpi_register_cb()
  • • 23.24.1 Simulation-event-related callbacks
    • 23.24.2 Simulation-time-related callbacks
    • 23.24.3 Simulator action and feature related callbacks
  • 23.25 vpi_register_systf()
  • • 23.25.1 System task and function callbacks
    • 23.25.2 Initializing VPI system task/function callbacks
  • 23.26 vpi_remove_cb()
  • 23.27 vpi_scan()
• Annex A Formal syntax definition
• • A.1 Source text
  • A.2 Declarations
  • A.3 Primitive instances
  • A.4 Module instantiation
  • A.5 UDP declaration and instantiation
  • A.6 Behavioral statements
  • A.7 Specify section
  • A.8 Expressions
  • A.9 General
• Annex B List of keywords
• Annex C The acc_user.h file
• Annex D The veriuser.h file
• Annex E The vpi_user.h file
• Annex F System tasks and functions
• • F.1 $countdrivers
  • F.2 $getpattern
  • F.3 $input
  • F.4 $key and $nokey
  • F.5 $list
  • F.6 $log and $nolog
  • F.7 $reset, $reset_count, and $reset_value
  • F.8 $save, $restart, and $incsave
  • F.9 $scale
  • F.10 $scope
  • F.11 $showscopes
  • F.12 $showvars
  • F.13 $sreadmemb and $sreadmemh
• Annex G Compiler directives
• • G.1 Ĭdefault_decay_time
  • G.2 Ĭdefault_trireg_strength
  • G.3 Ĭdelay_mode_distributed
  • G.4 Ĭdelay_mode_path
  • G.5 Ĭdelay_mode_unit
  • G.6 Ĭdelay_mode_zero
• Annex H Bibliography

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