IEEE Std 896.9-1994 IEEE Standard for Fault Tolerant Extensions to the Futurebus+^TM Architecture -Description

Abstract: This standard is one in a family of Futurebus+TM, standards. The Futurebus+ standards provide a set of tools with which to implement a bus architecture with performance and cost scalability over time for multiple generations of single- and multiple-bus multiprocessor systems. This standard provides fault tolerant extensions to Futurebus+ standards. As such, this standard provides the logical layer requirements for the transmission of data in a fault tolerant environment. When used in conjunction with other IEEE standards, the details to develop modular, open-architecture-based systems fulfilling user needs across a wide computing spectrum are available.

Keywords: bus, bus architecture, computers, data transmission, fault tolerance, Futurebus+, multiprocessor systems

Content

• 1. Overview
• • 1.1 Scope
  • 1.2 Purpose
  • 1.3 Fault tolerant system models
  • • 1.3.1 Fail-Stop
    • 1.3.2 Fail-Safe
    • 1.3.3 Fail-Operate
  • 1.4 Use of this standard
• 2. References
• 3. Definitions
• • 3.1 Special word usage
  • 3.2 Definitions for Futurebus+ systems
  • 3.3 Definitions for fault tolerant systems
  • 3.4 Syntax
  • • 3.4.1 CSR naming convention
    • 3.4.2 Numbering conventions
    • 3.4.3 CSR access types
• 4. Error detection
• • 4.1 Introduction
  • 4.2 Fault detection mechanisms
  • • 4.2.1 Parity
    • 4.2.2 Reflected protection
    • 4.2.3 Duplicated protection
    • 4.2.4 Protocol protection
    • 4.2.5 Timeout protection
• 5. Error handling
• • 5.1 Introduction
  • • 5.1.1 Error subclass
    • 5.1.2 Detection mechanism
    • 5.1.3 Detection phase
    • 5.1.4 Protected signals
    • 5.1.5 Error log snapshot
    • 5.1.6 Bus error signal
    • 5.1.7 Recovery strategy
    • 5.1.8 Retry strategy
    • 5.1.9 Containment strategy
  • 5.2 Error descriptions
  • • 5.2.1 Parity detection class
    • 5.2.2 Reflection detection class
    • 5.2.3 Duplication detection class
    • 5.2.4 Bus protocol detection class
    • 5.2.5 Counter expiration detection class
• 6. Error reports
• • 6.1 Introduction
  • 6.2 Snap groups
  • • 6.2.1 Master_Snap_Group
    • 6.2.2 Master_Snap_Group(Not_Principal)
    • 6.2.3 Master_Snap_Protocol
    • 6.2.4 Slave_Snap_Group
    • 6.2.5 Slave_Snap_Group(Master_Not_Principal)
    • 6.2.6 Slave_Snap_Protocol
  • 6.3 System notification
  • • 6.3.1 Slave_Assertion_Connection_Phase
    • 6.3.2 Slave_Assertion_Data_Phase
    • 6.3.3 Slave_Assertion_Disconnection_Phase
    • 6.3.4 Slave_Assertion_Protocol
    • 6.3.5 Slave_Assertion_Reflection_Error
    • 6.3.6 Slave_Assertion_Illegal_Operation
    • 6.3.7 Slave_Assertion_illegal_Operation_During_Discon nection
    • 6.3.8 Master_Assertion_Group
• 7. Error recovery
• • 7.1 Introduction
  • • 7.1.1 Master module
    • 7.1.2 Slave module
  • 7.2 Recovery strategies
  • • 7.2.1 Master recovery strategies
    • 7.2.2 Slave recovery strategies
    • 7.2.3 Bus_Init_Recovery
  • 7.3 Retry strategies
  • • 7.3.1 Master retry strategy
  • 7.4 Containment strategies
  • • 7.4.1 Module_Containment_Strategies
  • 7.5 Local error signal
  • • 7.5.1 Local_Report
  • 7.6 Alternate access
• 8. CSR definitions
• • 8.1 Introduction
  • 8.2 CSR summary
  • 8.3 ROM CSR extensions
  • • 8.3.1 NODE_CAPABILITIES_EXT CSR
  • 8.4 Futurebus+-dependent CSR extensions
  • • 8.4.1 Maintenance registers
    • 8.4.2 MAINT_UTILITY CSR
    • 8.4.3 WRITE_PROTECT CSR
    • 8.4.4 Timeout CSRs
  • 8.5 Core CSR extensions
  • • 8.5.1 ERROR_HI and ERROR_LO CSR
    • 8.5.2 Ancillary error CSRs
  • 8.6 Alternate access bus-specific CSRs
• Annex A Failure modes effects analysis
• • A.1 Introduction
  • A.2 Error detection mechanisms
  • • A.2.1 System requirements and assumptions
    • A.2.2 Protocol violation
    • A.2.3 Self-check
    • A.2.4 No-consequence errors and performance degradation
  • A.3 Failure mechanisms
  • • A.3.1 Module failures
    • A.3.2 Bus failures
    • A.3.3 Failures with no master selected
  • A.4 Analysis of individual bus lines

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