IEEE Std 896.4-1993 IEEE Standard for Conformance Test Requirements for Futurebus+ -Description
Abstract: A suite of abstract test cases for verifying the conformance of products based on the Futurebus+ family of standards and a means of selecting the exact set of test cases necessary for testing any given product are provided. The test suite is abstract in that it was not created with a specific test environment in mind. It can be effectively used in conjunction with logic simulators during product development as well as with physical testers after prototype or production units are available. This standard is intended for use by Futurebus+ product suppliers and users and by independent test labs. Consistent use of this standard should promote comparability and, therefore, mutual recognition of test results produced by different testers.
Keywords: application environment profile (AEP), BICS pro forma, BIXIT pro forma, block copy, implementation under test (IUT), interactive BICS
Content
1. Overview
1.1 Scope
1.2 Background
1.3 Terminology
2. References
3. Definitions
3.1 Definitions for bus lines and signals
3.2 Futurebus+ logo
4. Considerations for implementing a conformance test program
4.1 Physical tester
4.1.1 Logical tester model
4.1.2 Issues in implementing a physical tester
4.2 Executable test suite
4.2.1 Exhaustive vs. representative tests
4.2.2 Sequence-driven vs. requirement-driven
4.2.3 Monitor concept
4.2.4 Module initialization
4.2.5 Modification of code segments
4.3 Application of conformance tests
4.3.1 Testing CSRs
4.3.2 Testing modules with multiple subsystems
4.3.3 Data verification
4.4 Limitations of the conformance test process
4.4.1 Module testability
4.4.2 Conformance test vs. design verification
4.5 Test case format
4.6 Test case numbering scheme
4.6.1 Parallel protocol numbering scheme
4.6.2 Distributed arbitration numbering scheme
4.6.3 Central arbitration number scheme
4.6.4 Message passing numbering scheme
4.6.5 Bus/system management and CSR numbering scheme
5. Test cases
5.1 Parallel protocol
5.1.1 Read unlocked transaction
5.1.2 Write unlocked transaction
5.1.3 Address only unlocked transaction
5.1.4 Read locked transaction
5.1.5 Write locked transaction
5.1.6 Address only locked transaction
5.1.7 Read partial transaction
5.1.8 Write partial transaction
5.1.9 Read partial locked transaction
5.1.10 Write partial locked transaction
5.1.11 Read response transaction
5.1.12 Write response transaction
5.1.13 Write no acknowledge transaction
5.1.14 Read invalid transaction
5.1.15 Write invalid transaction
5.1.16 Copyback transaction
5.1.17 Read shared transaction
5.1.18 Read modified transaction
5.1.19 Invalidate transaction
5.1.20 Shared response transaction
5.1.21 Modified response transaction
5.1.22 Packet—read unlocked transaction
5.1.23 Packet—write unlocked transaction
5.1.24 Packet—read response transaction
5.2 Distributed arbitration
5.2.1 Basic functional testa
5.2.2 Extended functional tests
5.3 Central arbitration
5.3.1 Central arbitration requester
5.3.2 Central arbiter
5.4 Message passing
5.4.1 Frame level tests
5.4.2 Message level tests
5.5 CSR, bus/system management
5.5.1 Bus system management
5.5.2 Core CSRs
5.5.3 Futurebus+ specific CSRs
5.5.4 ROM tests
5.5.5 Tests for unimplemented registers
6. Monitors
6.1 Parallel protocol
6.1.1 Timing monitors
6.1.2 Protocol monitors
6.2 Distributed arbitration
6.2.1 Timing monitors
6.2.2 Protocol monitors
6.3 Central arbitration
6.3.1 Central arbitration requester monitors
6.3.2 Central arbiter monitors
6.4 Bus system management monitors
6.4.1 Bus initialize monitor
6.4.2 System reset monitor
7. General definitions for header file
8. Test case functions and prototypes
8.1 Function prototypes
8.2 Test case prototypes
8.3 C functions
9. BICS header file
10. Electrical test cases
10.1 Backplane signal skew
10.2 Module signal skew
Annex A BICS pro forma entry-to-test case mapping information
Annex B BICS pro forma
B.1 BICS pro forma
B.2 Generic bus implementation conformance statement for Futurebus, modules
B.2.1 General information
B.2.2 Instructions
B.2.3 Master characteristics
B.2.4 Slave characteristics
B.2.5 Split initiator characteristics
B.2.6 Split acceptor characteristics
B.2.7 Distributed arbitration characteristics
B.2.8 Central arbitration characteristics
B.2.9 Message passing characteristics
B.2.10 CSR support
B.2.11 Special considerations
B.2.12 Bus implementation extra information for testing (BIXIT) pro forma
