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IEEE Std 896.3-1993 IEEE Recommended Practice for Futurebus+ -Description

Abstract: The system layer issues associated with bus-based computer systems are described. It is intended to be a tool for Futurebus+ board and system designers. As such, the intent of this recommended practice is to characterize a variety of systems topics as they relate to Futurebus+. When used in conjunction with other IEEE standards, the details to develop modular, open-architecture-based systems fulfilling user needs across a wide computing spectrum are available. The specifications that may be required in conjunction with this recommended practice are: ISO/IEC 10857: 1994, IEEE Std 896.2-1991, IEEE Std 896.4-1993, IEEE Std 896.5-1993, IEEE Std 1149.1-1990, IEEE Std 1156.1-1993, IEEE Std 1194.1-1991, IEEE Std 1212-1991, IEEE Std 1212.1-1993, IEEE Std 1301.1-1991, and IEEE P1394/D6.8, March 1994.

Keywords: backplane bus, bus, bus architecture, Futurebus+, multiprocessor systems, shared memory systems

Content +

  • 1. Overview
    • 1.1 Scope
    • 1.2 Terminology
  • 2. References
  • 3. Definitions
    • 3.1 Definitions for bus lines and signals
    • 3.2 General definitions
    • 3.3 Futurebus+ logo
  • 4. Bus line description
    • 4.1 Information lines
      • 4.1.1 AD[63..0]* Address/Data lines
      • 4.1.2 D[255..64]* Data lines
      • 4.1.3 CM[7..0]*
      • 4.1.4 CP* Command parity
      • 4.1.5 ST[7..0]* Status
      • 4.1.6 CA[2..0]* Capability
      • 4.1.7 BP[31..0]* Bus parity
      • 4.1.8 TG[7..0]* Tag
      • 4.1.9 TP* Tag parity
    • 4.2 Synchronization lines
      • 4.2.1 AS* Address synchronization
      • 4.2.2 AK* Address acknowledge
      • 4.2.3 AI* Address acknowledge inverse
      • 4.2.4 DS* Data synchronization
      • 4.2.5 DK* Data acknowledge
      • 4.2.6 DI* Data acknowledge inverse
      • 4.2.7 ET* End of tenure
    • 4.3 Arbitrated message lines
      • 4.3.1 AB[7..0]* Arbitrated message bus
      • 4.3.2 ABP* Arbitrated message bus parity
      • 4.3.3 AP*, AQ*, AR* Arbitrated message synchronization
      • 4.3.4 AC[1..0]* Arbitrated message condition
    • 4.4 RE* Reset/Bus initialize
    • 4.5 Central arbiter
      • 4.5.1 PE* Preemption
      • 4.5.2 GR* Grant
      • 4.5.3 RQ[1..0]* Request
  • 5. System/Bus initialization
    • 5.1 Introduction
    • 5.2 System initialization and operation summary
      • 5.2.1 Operator interfaces
    • 5.3 Bus initialization
      • 5.3.1 System reset
      • 5.3.2 Module identification
      • 5.3.3 Built-in-self-test
      • 5.3.4 Configuration monarch selection
      • 5.3.5 Configuration monarch duties
      • 5.3.6 Operating system boot
  • 6. Byte lane mapping
    • 6.1 Introduction
    • 6.2 Endian history
      • 6.2.1 Endian-sensitive standards
      • 6.2.2 Data invariance
      • 6.2.3 Address invariance
      • 6.2.4 Hybrid endian
      • 6.2.5 Cross endian
    • 6.3 Addressan
      • 6.3.1 Futurebus-1987
      • 6.3.2 Futurebus+ evolution
    • 6.4 Futurebus+ addressan standard
      • 6.4.1 CSR registers
      • 6.4.2 Unit architecture
      • 6.4.3 Message passing
    • 6.5 Relabeling
      • 6.5.1 Little endian relabeling
      • 6.5.2 Big endian relabeling
    • 6.6 Multiplexers
      • 6.6.1 Big addressan multiplexers
  • 7. Fault management
    • 7.1 Introduction
    • 7.2 System fault management
      • 7.2.1 History unit
      • 7.2.2 Alternate access unit (AAU)
      • 7.2.3 Error handling
  • 8. Reliability and maintainability
    • 8.1 Introduction
    • 8.2 Reliability theory
    • 8.3 Part selection and control
    • 8.4 Derating
      • 8.4.1 Component failure rates
    • 8.5 Environmental design
    • 8.6 Failure modes and effects analysis (FMEA)
    • 8.7 EMI/RFI and ESD shielding
    • 8.8 Arbitration
      • 8.8.1 Distributed
      • 8.8.2 Central
    • 8.9 Live insertion
    • 8.10 Serial bus
    • 8.11 Redundancy
    • 8.12 Test architecture
      • 8.12.1 Partitioning
    • 8.13 Conformance testing
      • 8.13.1 Standardized conformance test documentation
      • 8.13.2 Conformance testing process overview
      • 8.13.3 Benefits of conformance testing
  • 9. System test
    • 9.1 Introduction
    • 9.2 Diagnostics and open systems
      • 9.2.1 Futurebus+ test goals
      • 9.2.2 Test hierarchy
      • 9.2.3 Test initiation
      • 9.2.4 Interface definitions
      • 9.2.5 TEST_STATE field
      • 9.2.6 Test sequence
      • 9.2.7 Remote diagnostics
      • 9.2.8 TAG link
      • 9.2.9 Supplemental diagnostics
      • 9.2.10 Optional utilities
      • 9.2.11 Diagnostic conventions supporting conformance testing
      • 9.2.12 Recommend test number assignment conventions
    • 9.3 Caused-All-Faults testing
      • 9.3.1 Fault detection
      • 9.3.2 Fault injection
      • 9.3.3 Fault reporting
    • 9.4 System verification/validation
  • 10. Serial bus
    • 10.1 Introduction
    • 10.2 Requirements
      • 10.2.1 Futurebus+ requirements
      • 10.2.2 Configuration requirements
      • 10.2.3 Fault-tolerant systems
      • 10.2.4 Testability
      • 10.2.5 Serial bus requirements summary
    • 10.3 Node design
    • 10.4 Serial bus specification
      • 10.4.1 Configuration requirements
      • 10.4.2 Futurebus+ compatibility
      • 10.4.3 Serial bus CSRs
      • 10.4.4 Module design
      • 10.4.5 Diagnostic interface
      • 10.4.6 Live insertion
  • 11. Futurebus+ Profile B bridge
    • 11.1 Scope
    • 11.2 Description
      • 11.2.1 Address mapping
      • 11.2.2 Transaction routing and translation
      • 11.2.3 Transaction arbitration priority
      • 11.2.4 Transaction ordering
      • 11.2.5 Flow control
      • 11.2.6 Starvation and Deadlock conditions
      • 11.2.7 Interrupts through bridges
      • 11.2.8 Bridge registers
      • 11.2.9 Prefetching and write buffering
  • 12. Dual bus architectures
    • 12.1 Introduction
    • 12.2 Backplane signals
    • 12.3 Operational modes
      • 12.3.1 Dual bus operations
      • 12.3.2 Concurrent bus operations
      • 12.3.3 Control and status
      • 12.3.4 Bus configuration
      • 12.3.5 Dual bus deadlock resolution
    • 12.4 Power supplies
      • 12.4.1 Battery backup
      • 12.4.2 Redundancy
      • 12.4.3 Live insertion
      • 12.4.4 Power distribution
  • 13. Real-time systems
    • 13.1 Introduction
    • 13.2 Priority-driven scheduling overview
      • 13.2.1 Hard and soft deadlines
      • 13.2.2 Rate-monotonic approach to real-time system design
      • 13.2.3 Estimating task execution times
      • 13.2.4 Arrival pattern of tasks
      • 13.2.5 Priority assignment to memory references and messages
      • 13.2.6 Advanced real-time scheduling issues
    • 13.3 Principles of priority management for real-time systems
      • 13.3.1 Priority-based resource allocation
      • 13.3.2 Sufficient and uniform priority granularities
      • 13.3.3 Managing priority queues
    • 13.4 Real-time scheduling support on the Futurebus+
      • 13.4.1 Priority arbitration on the Futurebus+
      • 13.4.2 Preemptive bus scheduling
      • 13.4.3 Control and status registers
      • 13.4.4 Futurebus+ message passing architecture
    • 13.5 Clock management
      • 13.5.1 Definitions, assumptions, and constraints
      • 13.5.2 Synchronization on a single bus
      • 13.5.3 Local clock adjustment
      • 13.5.4 Synchronization across multiple buses
    • 13.6 Predictable cache performance in real-time systems
      • 13.6.1 SMART cache partitioning
      • 13.6.2 Controlling the partitions
      • 13.6.3 Multiprocessors and predictable cache performance
    • 13.7 Software configuration guide
  • 14. Secure systems
    • 14.1 Introduction
    • 14.2 Approach
      • 14.2.1 Threats and risks
      • 14.2.2 Risk environments
    • 14.3 Security design issues
      • 14.3.1 Arbitration
      • 14.3.2 Parallel protocol
      • 14.3.3 Bus and system management
      • 14.3.4 Cache coherence
      • 14.3.5 Message passing
    • 14.4 Security service implementation
      • 14.4.1 Computer security
      • 14.4.2 Communication security
  • 15. Arbitration
    • 15.1 Introduction
      • 15.1.1 Terminology
      • 15.1.2 Arbitration requirements
    • 15.2 Distributed arbitration
      • 15.2.1 Multilevel priority
      • 15.2.2 Two-level priority
      • 15.2.3 Distributed arbitration messages
      • 15.2.4 Arbitration phases
      • 15.2.5 Comments
    • 15.3 Central arbitration
      • 15.3.1 Two-level priority
      • 15.3.2 Multilevel priority
      • 15.3.3 Comments
    • 15.4 Split transactions
    • 15.5 Physical aspects of central arbitration
  • 16. Measurements
    • 16.1 Introduction
    • 16.2 Data samples
      • 16.2.1 Trace data format
      • 16.2.2 Resource data format
      • 16.2.3 Raw data format
    • 16.3 Trace data source
      • 16.3.1 Time
      • 16.3.2 Node and CPU_ID
      • 16.3.3 Process_ID
      • 16.3.4 Event_ID
    • 16.4 Sampling
      • 16.4.1 Local sample
      • 16.4.2 Global sample
    • 16.5 Filter
    • 16.6 Sample data collection
  • Annex A Scheduling real-time tasks
    • A.1 Introduction
    • A.2 Periodic tasks
    • A.3 Stability under transient overload
    • A.4 Scheduling both aperiodic and periodic tasks
    • A.5 Task synchronization
    • A.6 Example application of the theory
    • A.7 Basic mechanisms for scheduling
  • Annex B Bibliography
    • B.1 Byte lane mapping references
    • B.2 Reliability and maintainability references
    • B.3 Serial bus references
    • B.4 Real-time references
    • B.5 Security references
    • B.6 Measurements references

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