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IEEE Std 896.10-1997 IEEE Standard for Futurebus+® Spaceborne Systems—Profile S -Description

Abstract: In the Futurebus+® series of standards, tools with which high-performance bus-based systems may be developed are provided. This architecture provides a wide range of performance scalability over both cost and time for multiple generations of single- and multiple-bus multiprocessor systems. This document, a companion standard to the 10857: 1994 (896.1, 1994 Edition) Futurebus+® Logical Layer Specification, builds on the logical layer by adding requirements for a spaceborne profile. It is to this profile that products will claim conformance. Other specifications may be required in conjunction with this standard.

Keywords: bus architecture, Futurebus+®, spaceborne computers, spaceborne modules, spaceborne systems

Content +

  • 1. Overview
    • 1.1 Scope
    • 1.2 Applicability
    • 1.3 Background to the standard
    • 1.4 Structure of the standard
    • 1.5 How to use this standard
    • 1.6 Why use this standard
  • 2. References
    • 2.1 Referenced documents
      • 2.1.1 IEEE standards
      • 2.1.2 Military standards
      • 2.1.3 EIA standards
    • 2.2 Conflicting standards
  • 3. Definitions
    • 3.1 Special word usage
    • 3.2 Bus line and signal conditions
    • 3.3 Futurebus+ terminology
    • 3.4 Conventions
    • 3.5 Syntax
    • 3.6 Futurebus+ logo
  • 4. Profile S reference specification
    • 4.1 Introduction
    • 4.2 Target applications
    • 4.3 Reference tables
    • 4.4 Profile S interoperability
    • 4.5 Conformance testing
  • 5. Detailed specification, Futurebus+ logical layer
    • 5.1 Arbitration
      • 5.1.1 Central arbitration
      • 5.1.2 Distributed arbitration
    • 5.2 Parallel protocol
      • 5.2.1 Transaction types
      • 5.2.2 Cache coherence
      • 5.2.3 Message passing
      • 5.2.4 Tag bits
  • 6. Utility Signals
    • 6.1 Trigger 0 (TR0*) and Trigger 1 (TR1*)
    • 6.2 Run (RUN*)
    • 6.3 Nuclear Event Detect (NED*)
    • 6.4 Power Failure Imminent (PFI*)
    • 6.5 Power Normal (PN)
    • 6.6 System Reset (SR*)
    • 6.7 Utility Spares (UPSP* and UWSP)
  • 7. Fault tolerance aspects of the parallel protocol and utility signals
    • 7.1 Error detection
      • 7.1.1 Even parity
      • 7.1.2 Error correcting codes
      • 7.1.3 Triple modular redundant (TMR) lines
      • 7.1.4 Duplicated signals
      • 7.1.5 Reflected protection
      • 7.1.6 Protocol monitoring
      • 7.1.7 Timeouts
    • 7.2 Error isolation, logging, and diagnostics
      • 7.2.1 Error handling
      • 7.2.2 Enable/Disable transceivers
      • 7.2.3 Force errors
      • 7.2.4 Diagnostic data register
      • 7.2.5 Critical register write protection
    • 7.3 Error removal and recovery
      • 7.3.1 Hardware retry
      • 7.3.2 Software retry
      • 7.3.3 Spare lines
      • 7.3.4 Dual Buses
    • 7.4 Pinout summary
  • 8. Serial Bus
    • 8.1 Serial Bus physical layer
    • 8.2 Serial Bus link layer
    • 8.3 Serial Bus transaction layer
  • 9. Bus/Node management and CSRs
    • 9.1 Addressing
    • 9.2 Byte-Lane wiring and byte ordering
    • 9.3 CSRs
    • 9.4 Futurebus+ CSRs
      • 9.4.1 Profile S core CSR extensions
      • 9.4.2 Profile S Futurebus+ specific CSR extensions
      • 9.4.3 Profile S ROM CSR extention
    • 9.5 Unit space CSRs
      • 9.5.1 Standard units
      • 9.5.2 Telemetry units
      • 9.5.3 Alternate access units
      • 9.5.4 Futurebus+ alternate access unit
      • 9.5.5 Serial bus alternate access unit
      • 9.5.6 Futurebus+ isolate control unit
    • 9.6 Serial Bus management
      • 9.6.1 Module design
      • 9.6.2 Other extensions
    • 9.7 Private space
    • 9.8 Interrupts
    • 9.9 Diagnostics and test
    • 9.10 Monarch selection
      • 9.10.1 Monarch selection process
  • 10. Detailed specification, physical layer—SEM-E Stretch
    • 10.1 Mechanical
      • 10.1.1 Unoccupied slots
      • 10.1.2 Backplane capacity
      • 10.1.3 Injector/Elector mechanism
    • 10.2 Input/Output
    • 10.3 Profile connector, power, and signal pin assignments
      • 10.3.1 Connector naming conventions and connector assignment
      • 10.3.2 Signal pin assignments
      • 10.3.3 Central arbiter definition
      • 10.3.4 Power pin assignments
      • 10.3.5 Connector keying
  • 11. Detailed specification, Physical layer—10 SU
    • 11.1 Mechanical
      • 11.1.1 Unoccupied slots
      • 11.1.2 Backplane capacity
      • 11.1.3 Injector/Elector mechanism
    • 11.2 Input/Output
    • 11.3 Profile connector, power, and signal pin assignments
      • 11.3.1 Connector naming conventions and connector assignment
      • 11.3.2 Signal pin assignments
      • 11.3.3 Central arbiter definition
      • 11.3.4 Power pin assignments
      • 11.3.5 Connector keying
  • 12. Profile S electrical
    • 12.1 Backplane characteristics and design requirements
      • 12.1.1 Geographical address lines
      • 12.1.2 Impedance
      • 12.1.3 Resistance
      • 12.1.4 Maximum propagation delay
      • 12.1.5 Termination
      • 12.1.6 Parallel protocol signal lines
      • 12.1.7 Central arbitration signal lines
    • 12.2 Module electrical characteristics and design requirements
      • 12.2.1 Geographical address lines
      • 12.2.2 Stub lengths
      • 12.2.3 Driver characteristics
      • 12.2.4 Switching voltage characteristics
      • 12.2.5 Wire-or driver glitch filtering
      • 12.2.6 Transceiver power-on and disabling
      • 12.2.7 Utility signals
      • 12.2.8 Extender cards
      • 12.2.9 Capacitive loading
  • 13. Profile S power
    • 13.1 Module power
      • 13.1.1 Power consumption limits
      • 13.1.2 Module bypass capacitance and di/dt
    • 13.2 Host system power supplies
      • 13.2.1 Power rails
      • 13.2.2 Rise time and power sequencing
      • 13.2.3 Voltage variation
      • 13.2.4 Overvoltage/Undervoltage limits
      • 13.2.5 Isolation
      • 13.2.6 Power supply peak current and di/dt capability
      • 13.2.7 Power fail
  • 14. Profile S environmental specifications
    • 14.1 System environmental requirements
    • 14.2 Module environmental requirements
  • 15. Recommended practices
    • 15.1 Thermal considerations
      • 15.1.1 Thermal analysis
      • 15.1.2 Reliability
      • 15.1.3 Structural considerations
    • 15.2 Power consumption
      • 15.2.1 Power control
    • 15.3 Pinouts
    • 15.4 Bus performance analysis
    • 15.5 Bandwidth considerations
      • 15.5.1 Multiple active bus masters
      • 15.5.2 Real-Time control
      • 15.5.3 Data producer/consumer
      • 15.5.4 Backplane data coherence systems
  • 16. Profile S module selection criteria
    • 16.1 Introduction
    • 16.2 Profile S modules
      • 16.2.1 Form, fit, and function
      • 16.2.2 Module power
      • 16.2.3 Environmental
    • 16.3 Profile S systems
  • 17. Alternate profile S module connector
    • 17.1 Mechanical
      • 17.1.1 Unoccupied slots
      • 17.1.2 Backplane capacity
      • 17.1.3 Injector/Elector mechanism
    • 17.2 Input/Output
    • 17.3 Profile connector, power, and signal pin assignments
      • 17.3.1 Connector naming conventions and connector assignment
      • 17.3.2 Signal pin assignments
      • 17.3.3 Central arbiter definition
      • 17.3.4 Power pin assignments
      • 17.3.5 Connector keying
      • 17.3.6 EMI shield pins
  • Annex A Bibliography

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