ANSI/IEEE Std 796-1983 IEEE Standard Microcomputer System Bus -Description

Content

• 1. General
• • 1.1 Scope
  • 1.2 Object
  • 1.3 Definitions
  • • 1.3.1 General System Terms
    • 1.3.2 Signals and Paths
• 2. Functional Description
• • 2.1 IEEE Std 796 Bus Elements
  • • 2.1.1 Masters
    • 2.1.2 Slaves
    • 2.1.3 IEEE Std 796 Bus Signals
  • 2.2 Data Transfer Operation
  • • 2.2.1 Data Transfer Overview
    • 2.2.2 Signal Descriptions
  • 2.3 Interrupt Operations
  • • 2.3.1 Interrupt Signal Lines
    • 2.3.2 Classes of Interrupt Implementation
  • 2.4 IEEE Std 796 Bus Exchange
  • • 2.4.1 IEEE Std 796 Bus Exchange Signals
    • 2.4.2 Bus Exchange Priority Techniques
• 3. Electrical Specifications
• • 3.1 General Bus Considerations
  • • 3.1.1 Logical and Electrical State Relationships
    • 3.1.2 Signal Line Characteristics
    • 3.1.3 Power Supply Specifications
    • 3.1.4 Temperature and Humidity
  • 3.2 Timing
  • • 3.2.1 Read Operations (I/O and Memory)
    • 3.2.2 Write Operations (I/O and Memory)
    • 3.2.3 Inhibit Operations
    • 3.2.4 Interrupt Implementations
    • 3.2.5 Bus Control Exchanges
    • 3.2.6 Miscellaneous Timing
  • 3.3 Receiver Modules, Driver Modules and Terminations
• 4. Mechanical Specifications
• • 4.1 Backplane Considerations
  • • 4.1.1 Board to Board Relationships
    • 4.1.2 IEEE Std 796 Bus Pin Assignments
  • 4.2 IEEE Std 796 Bus Board Form Factors
  • • 4.2.1 Connector Naming and Pin Numbering Standards
    • 4.2.2 Standard Outline of Printed Wiring Boards
    • 4.2.3 Bus Connectors
• 5. Levels of Compliance
• • 5.1 Variable Elements of Capability
  • • 5.1.1 Data Path
    • 5.1.2 Memory Address Path
    • 5.1.3 I/O Address Path
    • 5.1.4 Interrupt Attributes
  • 5.2 Masters and Slaves
  • 5.3 Compliance Level Notation
  • • 5.3.1 Data Path
    • 5.3.2 Memory Address Path
    • 5.3.3 I/O Address Path
    • 5.3.4 Interrupt Attributes
    • 5.3.5 An Example
    • 5.3.6 Compliance Marking
• 6. Bibliography

links: [Standard Status] - [Purchase] - [PDF^*] - [Bus Architecture Collection - Description]

available for Standards Online Bus Architecture Collection subscribers only