IEEE Std 1754-1994 IEEE Standard for a 32-bit Microprocessor Architecture -Description

Abstract: A 32-bit microprocessor architecture, available to a wide variety of manufacturers and users, is defined. The standard includes the definition of the instruction set, register model, data types, instruction opcodes, and coprocessor interface.

Keywords: computer, instruction set architecture, ISA, microprocessor

Content

• 1. Overview
• • 1.1 Scope
  • • 1.1.1 IEEE 1754 attributes
  • 1.2 IEEE 1754 system components
  • • 1.2.1 Reference MMU
    • 1.2.2 Supervisor software
  • 1.3 Binary compatibility
  • 1.4 IEEE 1754 features
  • 1.5 Conformance to IEEE 1754
  • 1.6 Conformance document
  • 1.7 References
• 2. Definitions, special word usage, abbreviations, and acronyms
• • 2.1 Definitions
  • 2.2 Special word usage
  • 2.3 Acronyms and abbreviations
• 3. Architectural overview
• • 3.1 IEEE 1754 processor
  • • 3.1.1 Integer unit (IU)
    • 3.1.2 Floating-point unit (FPU)
    • 3.1.3 Coprocessor (CP)
  • 3.2 Instructions
  • • 3.2.1 Memory access
    • 3.2.2 Arithmetic/logical/shift
    • 3.2.3 Control transfer
    • 3.2.4 State register access
    • 3.2.5 Floating-point operate (FPop)
    • 3.2.6 Coprocessor operate (CPop)
  • 3.3 Traps
• 4. Data formats
• • 4.1 Overview
  • 4.2 Signed integer byte
  • 4.3 Signed integer halfword
  • 4.4 Signed integer word
  • 4.5 Signed integer double
  • 4.6 Unsigned integer byte
  • 4.7 Unsigned integer halfword
  • 4.8 Unsigned integer word
  • 4.9 Unsigned integer double
  • 4.10 Unsigned tagged word
  • 4.11 Signed tagged word
  • 4.12 Floating-point single precision
  • 4.13 Floating-point double precision
  • 4.14 Floating-point quad precision
• 5. Registers
• • 5.1 IU r registers
  • • 5.1.1 Windowed r registers
    • 5.1.2 Overlapping of windows
    • 5.1.3 Special r registers
    • 5.1.4 Doubleword operands
    • 5.1.5 Register usage
  • 5.2 IU Control/status registers
  • • 5.2.1 Processor state register (PSR)
    • 5.2.2 Window invalid mask register (WIM)
    • 5.2.3 Trap base register (TBR)
    • 5.2.4 Multiply/divide register (Y)
    • 5.2.5 Program counters (PC, nPC)
    • 5.2.6 Ancillary state registers (ASR)
    • 5.2.7 Implementation-dependent extensions register
    • 5.2.8 IU deferred-trap queue
  • 5.3 FPU f registers
  • • 5.3.1 Double and quad operands
  • 5.4 FPU control/status registers
  • • 5.4.1 Floating-point state register (FSR)
    • 5.4.2 Floating-point exception fields
    • 5.4.3 FSR conformance
    • 5.4.4 Floating-point deferred-trap queue (FQ)
  • 5.5 CP registers
• 6. Instructions
• • 6.1 Instruction execution
  • 6.2 Instruction formats
  • • 6.2.1 Instruction fields
  • 6.3 Instruction categories
  • • 6.3.1 Memory access instructions
    • 6.3.2 Integer arithmetic instructions
    • 6.3.3 Control-transfer instructions (CTIs)
    • 6.3.4 SAVE instruction
    • 6.3.5 RESTORE instruction
    • 6.3.6 State register access
    • 6.3.7 Floating-point operate (FPop) instructions
    • 6.3.8 Coprocessor operate (CPop) instructions
    • 6.3.9 Reserved instructions
• 7. Traps
• • 7.1 Trap categories
  • • 7.1.1 Reset trap
    • 7.1.2 Precise trap
    • 7.1.3 Deferred trap
    • 7.1.4 Disrupting trap
  • 7.2 Trap model
  • 7.3 Trap control
  • • 7.3.1 ET and PIL control
    • 7.3.2 TEM control
  • 7.4 Trap identification
  • • 7.4.1 Trap type (tt)
    • 7.4.2 Trap priorities
  • 7.5 Trap definition
  • • 7.5.1 Reset trap
    • 7.5.2 Non-reset traps
    • 7.5.3 Error_state
    • 7.5.4 Processor execution state changes upon traps
  • 7.6 Exception/interrupt descriptions
  • 7.7 Trap actions
• Annex A Instruction definitions
• • A.1 Add instructions
• Format 3:
• Description:
• Traps:
• • A.1 Branch on coprocessor condition codes instructions
• Format 2:
• Description:
• Traps:
• • A.1 Branch on floating-point condition codes (FBfcc) instructions
• Format 2:
• Description:
• Traps:
• • A.1 Branch on integer condition codes (Bicc) instructions
• Format 3:
• Description:
• Traps:
• • A.1 Call and link instruction
• Format 1:
• Description:
• Traps:
• • A.1 Coprocessor operate instructions
• Format 3:
• Description:
• Traps:
• • A.1 Divide instructions (64 bit÷32 bit)
• Format 3:
• Description:
• Traps:
• • A.1 Floating-point add and subtract instructions
• Format 3:
• Description:
• Traps:
• • A.1 Floating-point compare instructions
• Format 3:
• Description:
• Traps:
• • A.1 Convert floating point to integer instructions
• Format 3:
• Description:
• Traps:
• • A.1 Convert between floating-point formats instructions
• Format 3:
• Description:
• Traps:
• • A.1 Convert integer to floating-point instructions
• Format 3:
• Description:
• Traps:
• • A.1 Floating-point move instructions
• Format 3:
• Description:
• Traps:
• • A.1 Floating-point multiply and divide instructions
• Format 3:
• Description:
• Traps:
• • A.1 Floating-point operate (FPop) instructions
• Format 3:
• Description:
• Traps:
• • A.1 Floating-point square-root instructions
• Format 3:
• Description:
• Traps:
• • A.1 Flush instruction memory
• Format 3:
• Description:
• Traps:
• • A.1 Jump and link instruction
• Format 3:
• Description:
• Traps:
• • A.1 Load coprocessor instructions
• Format 3:
• Description:
• Traps:
• • A.1 Load floating-point instructions
• Format 3:
• Description:
• Traps:
• • A.1 Load integer instructions
• Format 3:
• Description:
• Traps:
• • A.1 Load integer from alternate space instructions
• Format 3:
• Description:
• Traps:
• • A.1 Load-store unsigned byte instruction
• Format 3:
• Description:
• Traps:
• • A.1 Load-store unsigned byte in alternate space instruction
• Format 3:
• Description:
• Traps:
• • A.1 Logical instructions
• Format 3:
• Description:
• Traps:
• • A.1 Multiply instructions (32-bit)
• Format 3:
• Description:
• Traps:
• • A.1 Multiply step instruction
• Format 3:
• Description:
• Traps:
• • A.1 NOP instruction
• Format 2:
• Description:
• Traps:
• • A.1 Read state register instructions
• Format 3:
• Description:
• Traps:
• • A.1 Return from trap instruction
• Format 3:
• Description:
• Traps:
• • A.1 SAVE and RESTORE instructions
• Format 3:
• Description (effect on nonprivileged state:
• Traps:
• • A.1 SETHI instruction
• Format 2:
• Description:
• Traps:
• • A.1 Shift instructions
• Format 3:
• Description:
• Traps:
• • A.1 STBAR instruction
• Format 3:
• Description:
• Traps:
• • A.1 Store coprocessor instructions
• Format 3:
• Description:
• Traps:
• • A.1 Store floating-point instructions
• Format 3:
• Description:
• Traps:
• • A.1 Store integer instructions
• Format 3:
• Description:
• Traps:
• • A.1 Store integer into alternate space instructions
• Format 3:
• Description:
• Traps:
• • A.1 Subtract instructions
• Format 3:
• Description:
• Traps:
• • A.1 SWAP register with memory instruction
• Format 3:
• Description:
• Traps:
• • A.1 SWAP register with alternate space memory instruction
• Format 3:
• Description:
• Traps:
• • A.1 Tagged add instructions
• Format 3:
• Description
• Traps:
• • A.1 Tagged subtract instructions
• Format 3:
• Description:
• Traps:
• • A.1 Trap on integer condition codes instruction
• Format 3:
• Description:
• Traps:
• • A.1 Unimplemented instruction
• Format 2:
• Description:
• Traps:
• • A.1 Write state register instructions
• Format 3:
• Description:
• Traps:
• Annex B ISP descriptions
• • B.1 ISP notation
  • B.2 Processor external interface definition
  • • B.2.1 Interface macros
    • B.2.2 Interface signals
  • B.3 Register field definitions
  • B.4 Instruction field definitions
  • B.5 Temporary variable definitions
  • B.6 Processor states and instruction dispatch
  • B.7 Instruction dispatch
  • B.8 Floating-point execution
  • B.9 Traps
  • B.10 Instruction definitions
  • • B.10.1 Add instructions
    • B.10.2 Branch on integer condition instructions
    • B.10.3 CALL instruction
    • B.10.4 Coprocessor branch on condition instructions
    • B.10.5 Divide instructions
    • B.10.6 Floating-point branch on condition instructions
    • B.10.7 Flush instruction memory
    • B.10.8 Jump and link (JMPL) instruction
    • B.10.9 Load instructions
    • B.10.10 Load-store unsigned byte instructions
    • B.10.11 Logical instructions
    • B.10.12 Multiply instructions
    • B.10.13 Multiply step instruction
    • B.10.14 NOP instruction
    • B.10.15 Read state register instructions
    • B.10.16 Return from trap (RETT) instruction
    • B.10.17 SAVE and RESTORE instructions
    • B.10.18 SETHI instruction
    • B.10.19 Shift instructions
    • B.10.20 Store barrier instruction
    • B.10.21 Store instructions
    • B.10.22 Subtract instructions
    • B.10.23 Swap register with memory instructions
    • B.10.24 Tagged add instructions
    • B.10.25 Tagged subtract instructions
    • B.10.26 Trap on integer condition (Ticc) instructions
    • B.10.27 Unimplemented instruction
    • B.10.28 Write state register instructions
  • B.11 Floating-point operate instructions
  • • B.11.1 Convert between floating-point formats instructions
    • B.11.2 Convert floating-point to integer
    • B.11.3 Convert integer to floating-point instructions
    • B.11.4 Floating-point add and subtract instructions
    • B.11.5 Floating-point compare instructions
    • B.11.6 Floating-point move instructions
    • B.11.7 Floating-point multiply and divide instructions
    • B.11.8 Floating-point square root instructions
• Annex C IEEE 754 implementation requirements for IEEE 1754
• • C.1 Traps inhibit results
  • C.2 NaN operand and result definitions
  • • C.2.1 Untrapped floating-point result in different format than operands
    • C.2.2 Untrapped floating-point result in same format as operands
  • C.3 Trapped underflow definition (FSR.TEM.UFM=1)
  • C.4 Untrapped underflow definition (FSR.TEM.UFM=0)
  • C.5 Integer overflow definition
• Annex D IEEE 1754 implementation dependencies
• • D.1 Definition of an architectural implementation dependency
  • D.2 Hardware dependencies
  • D.3 Categories of architectural implementation dependencies
• Value (v):
• Assigned value (a):
• Functional choice (f):
• Total unit (t):
• Compatibility and miscellaneous issues (c):
• • D.4 List of implementation dependencies
  • D.1 Implementation dependency groups
  • • D.1.1 IU-related implementation dependencies
    • D.1.2 Coprocessor-related implementation dependencies
    • D.1.3 Floating-point-related implementation dependencies
    • D.1.4 Special registers and address space-related implementation dependencies
    • D.1.5 Trap-related implementation dependencies
    • D.1.6 MMU-related implementation dependencies
• Annex E Opcodes and condition codes
• Annex F IEEE 1754 Reference MMU architecture
• • F.1 Introduction
  • F.2 Overview
  • F.3 Software architecture
  • • F.3.1 Contexts
    • F.3.2 Page table descriptors (PTDs)
    • F.3.3 Page table entry (PTE)
    • F.3.4 MMU flush and probe model
  • F.4 Hardware architecture
  • • F.4.1 Accessing MMU registers
    • F.4.2 Control register
    • F.4.3 Context table pointer register
    • F.4.4 Context register
    • F.4.5 Diagnostic registers
  • F.5 MMU fault status register (MFSR)
  • F.6 MMU fault address register (MFAR)
  • F.7 Operation
  • • F.7.1 Reset
    • F.7.2 Miss processing
    • F.7.3 Referenced and modified bit updates
• Annex G Suggested ASI assignments
• • G.1 Introduction
  • G.2 ASI summary
  • G.3 Detailed descriptions
  • • G.3.1 ASI = 0 (reserved)
    • G.3.2 ASI = 1 (unassigned)
  • G.4 ASI = 2 (unassigned system registers)
  • • G.4.1 ASI = 3 (MMU flush/probe)
    • G.4.2 ASI = 4 (MMU registers)
    • G.4.3 ASI = 5 (MMU I diagnostic)
    • G.4.4 ASI = 6 (MMU D/I&D diagnostic)
    • G.4.5 ASI = 7 (MMU I/O diagnostic)
    • G.4.6 ASI = 8 (user I)
    • G.4.7 ASI = 9 (supervisor I)
    • G.4.8 ASI = A₁₆ (user D)
    • G.4.9 ASI = B₁₆ (supervisor D)
    • G.4.10 ASI = C₁₆ (I-cache tag)
    • G.4.11 ASI = D₁₆ (I-cache data)
    • G.4.12 ASI = E₁₆ (D/I&D-cache tag)
    • G.4.13 ASI = F₁₆ (D/I&D-cache data)
    • G.4.14 ASI = 10₁₆-14₁₆ (flush I&D)
    • G.4.15 ASI = 17₁₆ (block copy)
    • G.4.16 ASI = 1C₁₆ (flush I)
    • G.4.17 ASI = 1F₁₆ (block fill)
    • G.4.18 ASI = 20₁₆-2F₁₆ (pass-through)
    • G.4.19 ASI = 30₁₆-7F₁₆ (unassigned)
    • G.4.20 ASI = 80₁₆-FF₁₆ (reserved)
• Annex H Example integer multiplication and division routines
• • H.1 Signed multiplication
  • H.2 Unsigned multiplication
  • H.3 Division
  • • H.3.1 Program 1
    • H.3.2 Program 2
    • H.3.3 Program 3
    • H.3.4 Program 4
    • H.3.5 Program 5
    • H.3.6 Program 6
• Annex I Suggested assembly language syntax
• • I.1 Notation used
  • • I.1.1 Register names
    • I.1.2 Special symbol names
    • I.1.3 Values
    • I.1.4 Labels
    • I.1.5 Other operand syntax
    • I.1.6 Comments
  • I.2 Syntax design
  • I.3 Synthetic instructions
• Annex J Software considerations
• • J.1 Registers
  • • J.1.1 In and out registers
    • J.1.2 Local registers
    • J.1.3 Register windows and %sp
    • J.1.4 Global registers
    • J.1.5 Floating-point registers
  • J.2 The memory stack
  • J.3 Functions returning aggregate values
  • J.4 Tagged arithmetic
  • J.5 Leaf procedure optimization
  • J.6 Example code
  • J.7 Register allocation within a window
  • J.8 Other register window usage models
  • J.9 Non-IEEE 1754 modes of operation
  • J.10 Self-modifying code
• Annex K Instruction set summary
• • K.1 Introduction
  • K.2 Data transfer
  • K.3 Arithmetic and logical operations
  • K.4 Control transfer
  • K.5 Miscellaneous
  • K.6 Floating-point operations
• Annex L Non-IEEE 1754 architectural extensions
• • L.1 IEEE 1754 standard and non-standard operation
  • L.2 Addition of non-IEEE 1754 extensions
  • • L.2.1 Support for little-endian addressing
  • L.3 Modification of existing IEEE 1754 instructions
  • L.4 Extending IEEE 1754 to 64 bits
• Annex M Bibliography

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