IEEE Std 1596.4-1996 IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink) -Description

Abstract: A high-bandwidth interface optimized for interchanging data between a memory controller and one or more dynamic RAMs is specified. RamLink is an applicable interface for other RAM-like devices as well.

Keywords: dynamic RAMs, high-bandwidth, interface, RAM, RamLink

Content

• 1. Overview
• • 1.1 Scope
  • 1.2 Purpose
  • 1.3 Document structure
  • 1.4 Objectives
  • 1.5 Expected applications
  • • 1.5.1 Bulk memory controller
    • 1.5.2 Preconfigured uniprocessor
    • 1.5.3 Extendable uniprocessor
    • 1.5.4 Extendable multiprocessor
• 2. References
• 3. Definitions
• • 3.1 Conformance levels
  • 3.2 Definitions of RAM and interconnect-related terms
  • 3.3 Bit and byte ordering within packets
  • 3.4 Bit and byte ordering within CSRs
  • 3.5 Field notation (italics and bold usage)
  • 3.6 Numerical values
  • 3.7 Signaling layers
  • • 3.7.1 RingLink signaling
    • 3.7.2 SyncLink signaling
    • 3.7.3 RamLink illustrations
• 4. RamLink configurations
• • 4.1 Simple topologies
  • 4.2 Hierarchical topologies
  • 4.3 Hybrid signaling
  • 4.4 Wide (9-bit) data transfers
  • 4.5 DRAM error-checking options
  • • 4.5.1 Nonexistent ECC
    • 4.5.2 Controller-based ECC
    • 4.5.3 Controller-based parity
    • 4.5.4 Transparent ECC
  • 4.6 Link error-checking
  • • 4.6.1 Controller-generated parity
    • 4.6.2 Slave parity checking
    • 4.6.3 Slave-generated parity
• 5. RamLink operation
• • 5.1 Split-response transactions
  • 5.2 Response scheduling
  • 5.3 Retried transactions
  • 5.4 RamLink address space
  • 5.5 Address errors
  • 5.6 Request queue sizes
  • 5.7 Request ordering
  • 5.8 Refresh operations
  • • 5.8.1 Self-refresh
    • 5.8.2 Autorefresh
    • 5.8.3 Addressed refresh
  • 5.9 Rate adjustments
• 6. Packet formats
• • 6.1 Packet components
  • • 6.1.1 Packet framing
    • 6.1.2 Packet cmd values
    • 6.1.3 Data-block formats
    • 6.1.4 Check-byte values
  • 6.2 Request packet formats
  • • 6.2.1 Basic request packets
    • 6.2.2 Extended request packets
  • 6.3 Copy packet
  • 6.4 Event packets
  • • 6.4.1 Event packet format
    • 6.4.2 Event code values
    • 6.4.3 clockStrobe event
    • 6.4.4 Event processing time
  • 6.5 Response packets
  • • 6.5.1 Response packet format
    • 6.5.2 Standard sStat codes
    • 6.5.3 Vendor-dependent dStat values
  • 6.6 Retry packet format
  • 6.7 Idle packets
  • • 6.7.1 Controller-generated idles
  • 6.8 Special initialization packets
  • • 6.8.1 Sync packet formats
    • 6.8.2 Wait packet formats
    • 6.8.3 Wake packet formats
• 7. RamLink initialization
• • 7.1 standBy mode
  • 7.2 shutDown mode
  • 7.3 shutOff recovery
  • • 7.3.1 RamLink reset
    • 7.3.2 Slaveld assignments
  • 7.4 Self test and initialize
• Annex A Bibliography
• Annex B RingLink signaling
• • B.1 RingLink signals
  • B.2 RingLink connectivity
  • B.3 RingLink design model
  • B.4 RingLink driver/receiver circuits
  • B.5 RingLink shutdown sequences
  • • B.5.1 shutDown initiation
    • B.5.2 ShutDown recovery
    • B.5.3 clockRef design model
    • B.5.4 configHard assignments
    • B.5.5 Alarms
  • B.6 RingLink timing specifications
  • • B.6.1 Initialization-related parameters
    • B.6.2 Other timing parameters
  • B.7 RingLink signal levels
  • B.8 RingLink pinout
• Annex C SyncLink signals
• • C.1 SyncLink signals
  • C.2 SyncLink connectivity
  • C.3 Special linkOn considerations
  • C.4 SyncLink shutdown sequences
  • • C.4.1 shutdown initiation
    • C.4.2 shutDown recovery
    • C.4.3 configHard assignments
    • C.4.4 Alarms
• Annex D Control and status
• • D.1 CSR components
  • D.2 Bus-dependent ROM
  • • D.2.1 Minimal RamLink ROM format
    • D.2.2 rom_crc_value computation
    • D.2.3 RamLink-dependent info0 field
    • D.2.4 RamLink-dependent info1 field
    • D.2.5 Vendor-dependent ROM information
    • D.2.6 company_id assignments
  • D.3 RamLink transaction set
  • D.4 CSR Architecture defined registers
  • • D.4.1 STATE_CLEAR register
    • D.4.2 NODE_IDS register
    • D.4.3 SPLIT_TIMEOUT register
    • D.4.4 ARGUMENT registers
  • D.5 Bus-dependent CSRs
  • • D.5.1 ERROR_COUNT register
  • D.6 Synchronizing time-of-day clocks
  • • D.6.1 RamLink-local synchronization
    • D.6.2 Synchronizing to slave reference-clock
• Annex E I/O extensions
• • E.1 Power-on signaling
  • E.2 I/O device models
  • • E.2.1 Memory-mapped I/O (frame buffer)
    • E.2.2 DMA I/O device (disk controller)
    • E.2.3 Bus bridge (a delayed responder)
  • E.3 Subaction-entry processing
  • • E.3.1 DMA accessing RamLink memory
    • E.3.2 DMA accessing remote register
    • E.3.3 Remote access of RamLink memory
    • E.3.4 Output-queue processing
    • E.3.5 Output-queue processing
  • E.4 Queue-index registers
  • • E.4.1 Addressable-FIFO queues
    • E.4.2 Requester-queue formats
    • E.4.3 Bridge queue formats
  • E.5 Common subaction-entry fields
  • • E.5.1 Subaction formats
    • E.5.2 Subaction cmds
    • E.5.3 stamp field components
    • E.5.4 ids field components
  • E.6 Request-subaction entries
  • • E.6.1 Request-subaction fields
    • E.6.2 Read-request hints
    • E.6.3 write 16 request
    • E.6.4 write64 request
    • E.6.5 write256 request
    • E.6.6 Read and control requests
    • E.6.7 Lock requests
  • E.7 Response-subaction format
  • • E.7.1 Response-subaction fields
    • E.7.2 Response subaction hints
    • E.7.3 Write and control responses
    • E.7.4 Lock and read16 responses
    • E.7.5 read64 response
    • E.7.6 read256 response
  • E.8 Narrowcast selection
  • • E.8.1 Idle select-loop behavior
    • E.8.2 Slave's alarm assertion
    • E.8.3 Controller's alarm reception
  • E.9 Potential extensions
  • • E.9.1 Cache-coherent bridges
    • E.9.2 Homogeneous-bridge transfers

links: [Standard Status] - [Purchase] - [PDF^*] - [Bus Architecture Collection - Description]

available for Standards Online Bus Architecture Collection subscribers only