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IEEE Std 1596.3-1996 IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI) -Description

Abstract: Scalable Coherent Interface (SCI), specified in IEEE Std 1596-1992, provides computer-bus-like services but uses a collection of fast point-to-point links instead of a physical bus in order to reach far higher speeds. The base specification defines differential ECL signals, which provide a high transfer rate (16 bits are transferred every 2 ns), but are inconvenient for some applications. IEEE Std 1596.3-1996, an extension to IEEE Std 1596-1992, defines a lower-voltage differential signal (as low as 250 mV swing) that is compatible with low-voltage CMOS, BiCMOS, and GaAs circuitry. The power dissipation of the transceivers is low, since only 2.5 ω mA is needed to generate this differential voltage across a 100 termination resistance. Signal encoding is defined that allows transfer of SCl packets over data paths that are 4-, 8-, 32-, 64-, and 128-bits wide. Narrow data paths (4 to 8 bits) transferring data every 2 ns can provide sufficient bandwidth for many applications while reducing the physical size and cost of the interface. The wider paths may be needed for very-high-performance systems.

Keywords: backplane, bus, cable, differential, low-power, point-to-point, scalable, signal

Content +

  • 1. Overview
    • 1.1 Scope
    • 1.2 Objectives
    • 1.3 Strategies
    • 1.4 Design models
      • 1.4.1 Source-synchronous data
      • 1.4.2 Terminated transmission lines
  • 2. Document notation
    • 2.1 Conformance levels
    • 2.2 Technical glossary
  • 3. Electrical specifications
    • 3.1 Description and configuration
    • 3.2 Electrical specifications
      • 3.2.1 Driver output levels
      • 3.2.2 Driver short-circuit specification
      • 3.2.3 AC driver-output impedance
      • 3.2.4 DC driver-output impedance
      • 3.2.5 Driver power-off leakage current
      • 3.2.6 Receiver input levels
      • 3.2.7 Receiver input impedance
      • 3.2.8 Receiver threshold hysteresis
    • 3.3 AC specifications
      • 3.3.1 Driver transition times and undershoot
      • 3.3.2 Receiver common-mode rejection
    • 3.4 Skew specifications
  • Annex A Bibliography
  • Annex B SCI signal encoding
    • B.1 SCI symbol encoding
    • B.2 Narrow parallel encoding
      • B.2.1 Parallel 8/10 (P10) encoding
      • B.2.2 Parallel 4/5 (P5) encoding
    • B.3 Wide parallel encoding
      • B.3.1 Parallel 32/36 (P36) encoding
      • B.3.2 Parallel 64/70 (P70) encoding
      • B.3.3 Parallel 128/138 (P138) encoding
  • Annex C Driver and receiver models
    • C.1 Driver model
    • C.2 Receiver model
    • C.3 Signal transmission model

links: [Standard Status] - [Purchase] - [PDF*] - [Bus Architecture Collection - Description]

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