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IEEE Std 1596-1992 IEEE Standard for Scalable Coherent Interface (SCI) -Description

Abstract: The scalable coherent interface (SCI) provides computer-bus-like services but, instead of a bus, uses a collection of fast point-to-point unidirectional links to provide the far higher throughput needed for high-performance multiprocessor systems. SCI supports distributed, shared memory with optional cache coherence for tightly coupled systems, and message-passing for loosely coupled systems. Initial SCI links are defined at 1 Gbyte/s (16-bit parallel) and 1 Gb/s (serial). For applications requiring modular packaging, an interchangeable module is specified along with connector and power. The packets and protocols that implement transactions are defined and their formal specification is provided in the form of computer programs. In addition to the usual read-and-write transactions, SCI supports efficient multiprocessor lock transactions. The distributed cache-coherence protocols are efficient and can recover from an arbitrary number of transmission failures. SCI protocols ensure forward progress despite multiprocessor conflicts (no deadlocks or starvation).

Keywords: bus architecture, bus standard, cache coherence, distributed memory, fiber optic, interconnect, I/O system, link, mesh, multiprocessor, network, packet protocol, ring, seamless distributed computer, shared memory, switch, transaction set

Content +

  • 1. Introduction
    • 1.1 Document structure
    • 1.2 SCI overview
      • 1.2.1 Scope and directions
      • 1.2.2 The SCI approach
      • 1.2.3 System configurations
      • 1.2.4 Initial physical models
      • 1.2.5 SCI node model
      • 1.2.6 Architectural parameters
      • 1.2.7 A common CSR architecture
      • 1.2.8 Structure of the specification
    • 1.3 Interconnect topologies
      • 1.3.1 Bridged systems
      • 1.3.2 Scalable systems
      • 1.3.3 Interconnected systems
      • 1.3.4 Backplane rings
      • 1.3.5 Interconnected rings
      • 1.3.6 Rectangular grid interconnects
      • 1.3.7 Butterfly switches
      • 1.3.8 Vendor-dependent switches
    • 1.4 Transactions
      • 1.4.1 Packet formats
      • 1.4.2 Input and output queues
      • 1.4.3 Request and response queues
      • 1.4.4 Switch queues
      • 1.4.5 Subactions
      • 1.4.6 Remote transactions (through agents)
      • 1.4.7 Move transactions
      • 1.4.8 Broadcast moves
      • 1.4.9 Broadcast passing by agents
      • 1.4.10 Transaction types
      • 1.4.11 Message passing
      • 1.4.12 Global clocks
      • 1.4.13 Allocation protocols
      • 1.4.14 Queue allocation
    • 1.5 Cache coherence
      • 1.5.1 Interconnect constraints
      • 1.5.2 Distributed directories
      • 1.5.3 Standard optimizations
      • 1.5.4 Future extensions
      • 1.5.5 TLB purges
    • 1.6 Reliability, availability, and support (RAS)
      • 1.6.1 RAS overview
      • 1.6.2 Autoconfiguration
      • 1.6.3 Control and status registers
      • 1.6.4 Transmission-error detection and isolation
      • 1.6.5 Error containment
      • 1.6.6 Hardware fault retry (ringlet-local, physical layer option)
      • 1.6.7 Software fault recovery (end-to-end)
      • 1.6.8 System debugging
      • 1.6.9 Alternate routing
      • 1.6.10 Online replacement
  • 2. References, glossary, and notation
    • 2.1 References
    • 2.2 Conformance levels
    • 2.3 Glossary
    • 2.4 Bit and byte ordering
    • 2.5 Numerical values
    • 2.6 C code
  • 3. Logical protocols and formats
    • 3.1 Packet formats
      • 3.1.1 Packet types
    • 3.2 Send and echo packet formats
      • 3.2.1 Request-send packet format
      • 3.2.2 Request-echo packet format
      • 3.2.3 Response-send packet
      • 3.2.4 Standard status codes
      • 3.2.5 Response-echo packet format
      • 3.2.6 Interconnect-affected fields
      • 3.2.7 Init packets
      • 3.2.8 Cyclic redundancy code (CRC)
      • 3.2.9 Parallel 16-bit CRC calculations
      • 3.2.10 CRC stomping
      • 3.2.11 Idle symbols
    • 3.3 Logical packet encodings
      • 3.3.1 Flag coding
    • 3.4 Transaction types
      • 3.4.1 Transaction commands
      • 3.4.2 Lock subcommands
      • 3.4.3 Unaligned DMA transfers
      • 3.4.4 Aligned block-transfer hints
      • 3.4.5 Move transactions
      • 3.4.6 Global time synchronization
    • 3.5 Elastic buffers
      • 3.5.1 Elasticity models
      • 3.5.2 Idle-symbol insertions
      • 3.5.3 Idle-symbol deletions
    • 3.6 Bandwidth allocation
      • 3.6.1 Fair bandwidth allocation
      • 3.6.2 Setting ringlet priority
      • 3.6.3 Bandwidth partitioning
      • 3.6.4 Types of transmission protocols
      • 3.6.5 Pass-transmission protocol
      • 3.6.6 Low-transmission protocol
      • 3.6.7 Idle insertions
      • 3.6.8 High-transmission protocol
    • 3.7 Queue allocation
      • 3.7.1 Queue reservations
      • 3.7.2 Multiple active sends
      • 3.7.3 Unfair reservations
      • 3.7.4 Queue-selection protocols
      • 3.7.5 Re-send priorities
    • 3.8 Transaction errors
      • 3.8.1 Requester timeouts (response-expected packets)
      • 3.8.2 Time-of-death timeout (optional, all nodes)
      • 3.8.3 Responder-processing errors
    • 3.9 Transmission errors
      • 3.9.1 Error isolation
      • 3.9.2 Scrubber maintenance
      • 3.9.3 Producer-detected errors
      • 3.9.4 Consumer-detected errors
    • 3.10 Address initialization
      • 3.10.1 Transaction addressing
      • 3.10.2 Reset types
      • 3.10.3 Unique node identifiers
      • 3.10.4 Ringlet initialization
      • 3.10.5 Simple-subset ringlet resets
      • 3.10.6 Ringlet resets
      • 3.10.7 Ringlet clears (optional)
      • 3.10.8 Inserting initialization packets
      • 3.10.9 Address initialization
    • 3.11 Packet encoding
      • 3.11.1 Common encoding features (L18)
      • 3.11.2 Parallel encoding with 18 signals (P18)
      • 3.11.3 Serial encoding with 20-bit symbols (S20)
    • 3.12 SCI-specific control and status registers
      • 3.12.1 SCI transaction sets
      • 3.12.2 SCI resets
      • 3.12.3 SCI-dependent fields within standard CSRs
      • 3.12.4 SCI-dependent CSRs
      • 3.12.5 SCI-dependent ROM
      • 3.12.6 Interrupt register formats
      • 3.12.7 Interleaved logical addressing
  • 4. Cache-coherence protocols
    • 4.1 Introduction
      • 4.1.1 Objectives
      • 4.1.2 SCI transaction components
      • 4.1.3 Physical addressing
      • 4.1.4 Coherence directory overview
      • 4.1.5 Memory and cache tags
      • 4.1.6 Instruction-execution model
      • 4.1.7 Coherence document structure
    • 4.2 Coherence update sequences
      • 4.2.1 List prepend
      • 4.2.2 List-entry deletion
      • 4.2.3 Update actions
      • 4.2.4 Cache-line locks
      • 4.2.5 Stable sharing lists
    • 4.3 Minimal-set coherence protocols
      • 4.3.1 Sharing-list updates
      • 4.3.2 Cache fetching
      • 4.3.3 Cache rollouts
      • 4.3.4 Instruction-execution model
    • 4.4 Typical-set coherence protocols
      • 4.4.1 Sharing-list updates
      • 4.4.2 Read-only fetch
      • 4.4.3 Read-write fetch
      • 4.4.4 Data modifications
      • 4.4.5 Mid and head deletions
      • 4.4.6 DMA reads and writes
      • 4.4.7 Instruction-execution model
    • 4.5 Full-set coherence protocols
      • 4.5.1 Full-set option summary
      • 4.5.2 CLEAN-list creation
      • 4.5.3 Sharing-list additions
      • 4.5.4 Cache washing
      • 4.5.5 Cache flushing
      • 4.5.6 Cache cleansing
      • 4.5.7 Pairwise sharing
      • 4.5.8 Pairwise-sharing faults
      • 4.5.9 QOLB sharing
      • 4.5.10 Cache-access properties
      • 4.5.11 Instruction-execution model
    • 4.6 C-code naming conventions
    • 4.7 Coherent read and write transactions
      • 4.7.1 Extended mread transactions
      • 4.7.2 Cache cread and cwrite64 transactions
      • 4.7.3 Smaller tag sizes
  • 5. C-code structure
    • 5.1 Node structure
      • 5.1.1 Signals within a node
      • 5.1.2 Packet transfers among node components
      • 5.1.3 Transfer-cloud components
    • 5.2 A node's linc component
      • 5.2.1 A linc's subcomponents
      • 5.2.2 A linc's elastic buffer
      • 5.2.3 Other linc components
    • 5.3 Other node components
      • 5.3.1 A node's core component
      • 5.3.2 A node's memory component
      • 5.3.3 A node's exec component
      • 5.3.4 A node's proc component
  • 6. Physical layers
    • 6.1 Type 1 module
      • 6.1.1 Module characteristics
      • 6.1.2 Module compatibility considerations
      • 6.1.3 Module size
      • 6.1.4 Warpage, bowing, and deflection
      • 6.1.5 Cooling
      • 6.1.6 Connector
      • 6.1.7 Power and ground connection
      • 6.1.8 Pin allocation for backplane parallel 18-signal encoding
      • 6.1.9 Slot-identification signals
    • 6.2 Type 18-DE-500 signals and power control
      • 6.2.1 SCI differential signals
      • 6.2.2 Status lines
      • 6.2.3 Serial Bus signals
      • 6.2.4 Signal levels and skew
      • 6.2.5 Power-conversion control
    • 6.3 Type 18-DE-500 module extender cable
    • 6.4 Type 18-DE-500 cable-link
    • 6.5 Serial interconnection
      • 6.5.1 Serial interface Type 1-SE-1250, single-ended electrical
      • 6.5.2 Optical interface, fiber-optic signal type 1-FO-1250
      • 6.5.3 Test methods
  • 7. Bibliography
  • Annex A Ringlet initialization
  • Annex B SCI design models
    • B.1 Fast counters
    • B.2 Translation-lookaside-buffer coherence
      • B.2.1 Virtual addressing
      • B.2.2 TLB-purge options
      • B.2.3 Interrupt-driven purges
      • B.2.4 Direct-register purges
      • B.2.5 Coherently purged TLBs
    • B.3 Coherent lock models
    • B.4 Coherence-performance models
      • B.4.1 Nonblocking message queues

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