IEEE Std 1496-1993 IEEE Standard for a Chip and Module Interconnect
Bus: SBus -Description
Abstract: An input/output
expansion bus with a 32- or 64-bit width is described in this standard.
The SBus is designed for systems requiring a small number of expansion
ports. SBus Cards may be connected to a standard SBus Connector
mounted on the motherboard. SBus Devices may also be attached to
the SBus directly on the system"s motherboard. The dimensions
of the SBus Card are 83.8 mm by 146.7 mm, making the cards appropriate
for small computer systems that make extensive use of highly integrated
circuits. The SBus Cards are designed to be installed in a plane
parallel to the system"s motherboard as mezzanine cards.
They are designed to provide connections for devices external to
the computer system through an exposed back panel. The form factor
is useful in Futurebus+, VMEbus, desktop computers, and
similar applications. The SBus has the capability of transferring
data at rates up to 168 Mbytes/s, depending on the implementation
options selected.SBus Cards may either serve as Masters on the
bus, providing all virtual address information as well as the data
to be transferred, or they may serve as Slaves on the bus, providing
data transfer according to the requirements of some other SBus Master.
The SBus Master for a data transfer is selected by an arbitration process
managed by the single SBus Controller on the SBus. The SBus Controller
provides a virtual to physical address translation service.
Keywords: I/O
bus, SBus, SBus Card, Standard
for Boot Firmware
Content
1. Introduction
1.1 Scope
1.2 Purpose
1.3 Reference
2. Definitions,
usage of special terms, acronyms, and editorial conventions
2.1 Definitions
2.2 Usage of
special terms
2.3 Acronyms
2.4 Editorial
conventions
2.4.1 Signal names
2.4.2 Numbers
2.4.3 Physical
dimensions
3. Overview
3.1 System overview
3.1.1 SBus Master
3.1.2 SBus Controller
3.1.3 SBus Slave
3.2 Overview
of configurations
3.2.1 Symmetric
SBus cycles
3.2.2 Asymmetric
SBus cycles
3.2.3 Multiple
SBus Systems
3.3 General
design information
3.3.1 Protocol
control
3.3.2 Bus driving
3.4 Performance
3.4.1 Clock rates
3.4.2 Transfer
rates
3.4.3 Latency
4. Signal definitions
4.1 CLK signal
4.2 RST* signal
4.3 PA[27:0] signals
4.4 SEL* signal
4.5 AS* signal
4.6 BR* signal
4.7 BG* signal
4.8 D[31:0],
D[63:0], and DP signals
4.9 SlZ[2:0] signals
4.10 RD signal
4.11 ACK[2:0]* signals
4.12 LERR* signal
4.13 INT[7:1]* signals
5. SBus cycle
definitions
5.1 Arbitration
Phase
5.2 Translation
Phase
5.3 Extended
Transfer Information Phase
5.3.1 Extended
Type field
5.3.2 Extended
Transfer Count field
5.3.3 Extended
Read field
5.3.4 Extended
Lock field
5.4 Transfer
Phase
5.4.1 32-bit Transfer
Phase
5.4.2 64-bit Extended
Transfer Phase
5.4.3 Data size
and Acknowledgments
5.4.4 Burst Transfers
5.4.5 Data organization
5.4.6 Bus Sizing
5.4.7 Parity checking
5.4.8 Retry Acknowledgment
5.4.9 Error Acknowledgment
during Transfer Phase
5.5 Dual function
SBus Devices
5.6 Exception
conditions
5.6.1 Late Error
5.6.2 Timeouts
5.6.3 Interrupts
5.7 Extended
Transfer locking protocol
5.7.1 Description
of Bus Locking
5.7.2 SBus Bus
Locking protocol
6. SBus electrical
requirements
6.1 Power
6.1.1 SBus Card
power
6.2 Electronic
characteristics
6.2.1 Capacitive
loading requirements
6.2.2 Printed
wire length requirements
6.2.3 Signal bias
circuits
6.2.4 DC parameters
6.3 Electronic
timing requirements
6.3.1 AC parameters
and measurements
6.3.2 Specification
of clock skew
6.3.3 Specification
of input timing requirements
6.3.4 Specification
of output timing requirements
6.4 Compliance
requirements
7. Environmental
requirements
7.1 Operating
range
8. Mechanical
requirements
8.1 SBus Slot
Connector
8.2 SBus Card
8.2.1 Board materials
8.2.2 Component
clearance
8.2.3 Backplate
8.2.4 Single-wide
board and backplate
8.2.5 Double-wide
board
8.2.6 Retention
and standoff
8.3 Panel installation
9. SBus program
interface
9.1 Introduction
9.2 Program
format and interpretation
9.3 Required
FCode attributes
9.4 FCode language
9.5 Special
functions of Word 0
9.5.1 Read operations
to Word 0
9.5.2 Write operations
to Word 0
Annex A Bibliography
Annex B Compliance checklist
B.1 SBus Master
B.1.1 SBus Master
compliance check list
B.1.2 SBus Master
options
B.2 SBus Slave
B.2.1 SBus Slave
compliance check list
B.2.2 SBus Slave
options
B.3 SBus Controller
B.3.1 SBus Controller
compliance check list
B.3.2 SBus Controller
options
B.4 SBus Card
B.4.1 SBus Card
compliance check list
B.4.2 SBus Card
options
B.5 SBus System
B.5.1 SBus System
compliance check list
B.5.2 SBus System
options
Annex C Known implementation
variations
C.1 PA[27:0] signals
not completely driven by some early SBus Controllers
C.2 SIZ[2:0] signals
incompletely supported by early SBus Controllers
C.3 Padded Data
Acknowledgment after Error Acknowledgment
C.4 Usual interpretation
of LERR* signal
C.5 Extended
Transfer Information Phase negation of RD
