ISO/IEC 14536 : 1995 [ANSI/IEEE Std 896.5, 1995 Edition] Information technology— Microprocessor systems— Futurebus+™, Profile M (Military) -Description

Content

• 1. Overview
• • 1.1 Scope
  • 1.2 Applicability
• 2. Normative references
• 3. Definitions
• • 3.1 Special word usage
  • 3.2 General definitions
• 4. Military Profile MIL-12SU
• • 4.1 Reference specification
  • • 4.1.1 Introduction
    • 4.1.2 Target usage
    • 4.1.3 Reference tables
    • 4.1.4 Applicable standards and profile terminology
  • 4.2 Logical layer detailed specifications
  • • 4.2.1 Arbitration protocol
    • 4.2.2 Parallel protocol
    • 4.2.3 Caching and cache coherence
    • 4.2.4 Message passing
    • 4.2.5 Tag bits
    • 4.2.6 Serial Bus
    • 4.2.7 Utility signals
    • 4.2.8 Local interconnects
    • 4.2.9 Input/output
    • 4.2.10 User-defined clock
  • 4.3 Bus and node management
  • • 4.3.1 Addressing
    • 4.3.2 Byte-lane mapping
    • 4.3.3 CSRs
    • 4.3.4 Private space
    • 4.3.5 Interrupts
    • 4.3.6 Monarch selection
    • 4.3.7 System initialization
    • 4.3.8 Direct memory access (DMA)
    • 4.3.9 Diagnostics and test
    • 4.3.10 Live insertion and withdrawal
  • 4.4 Physical layer detailed specification
  • • 4.4.1 Profile power
    • 4.4.2 Electrical profile
    • 4.4.3 Mechanical
    • 4.4.4 Input/output
    • 4.4.5 Backplane capacity
    • 4.4.6 Profile connector, power and signal pin assignments
  • 4.5 Environmental
  • • 4.5.1 System environmental requirements
    • 4.5.2 Module environmental requirements
  • 4.6 Systems configuration guide
  • 4.7 Conformance testing
• 5. Military Profile MIL-10SU
• • 5.1 Reference specification
  • • 5.1.1 Introduction
    • 5.1.2 Target usage
    • 5.1.3 Reference tables
    • 5.1.4 Applicable standards and profile terminology
  • 5.2 Logical layer detailed specification
  • • 5.2.1 Arbitration protocol
    • 5.2.2 Parallel protocol
    • 5.2.3 Caching and cache coherence
    • 5.2.4 Message passing
    • 5.2.5 Tag bits
    • 5.2.6 Serial Bus
    • 5.2.7 Utility signals
    • 5.2.8 Local interconnects
    • 5.2.9 Input/output
    • 5.2.10 User-defined clock
  • 5.3 Bus and node management
  • 5.4 Physical layer detailed specification
  • • 5.4.1 Profile power
    • 5.4.2 Profile electrical
    • 5.4.3 Mechanical
    • 5.4.4 Input/output
    • 5.4.5 Backplane capacity
    • 5.4.6 Profile connector, power and signal pin assignments
  • 5.5 Environmental
  • • 5.5.1 System environmental requirements
    • 5.5.2 Module environmental requirements
  • 5.6 Systems configuration guide
  • 5.7 Conformance testing
• 6. Military Profile MIL-Format E
• • 6.1 Reference specification
  • • 6.1.1 Introduction
    • 6.1.2 Target usage
    • 6.1.3 Reference tables
    • 6.1.4 Applicable standards and profile terminology
  • 6.2 Logical layer detailed specification
  • • 6.2.1 Arbitration protocol
    • 6.2.2 Parallel protocol
    • 6.2.3 Caching and cache coherence
    • 6.2.4 Message passing
    • 6.2.5 Tag bits
    • 6.2.6 Serial Bus
    • 6.2.7 Utility signals
    • 6.2.8 Local interconnects
    • 6.2.9 Input/output
    • 6.2.10 User-defined clock
    • 6.2.11 Reserved field
  • 6.3 Bus and node management
  • 6.4 Physical layer detailed specification
  • • 6.4.1 Profile power
    • 6.4.2 Profile electrical
    • 6.4.3 Mechanical
    • 6.4.4 Input/output
    • 6.4.5 Backplane capacity
    • 6.4.6 Profile connector, power and signal pin assignments
  • 6.5 Environmental
  • • 6.5.1 System environmental requirements
    • 6.5.2 Module environmental requirements
  • 6.6 System configuration guide
  • 6.7 Conformance testing
• Annex A Military-specific standard units
• • A.1 Software development unit
  • • A.1.1 Introduction
    • A.1.2 Program control (non-real time functions)
    • A.1.3 Real time non-intrusive instrumentation (RTNI) functions
    • A.1.4 UCIF interface CSR description
    • A.1.5 Performance monitoring functions
  • A.2 History units
  • • A.2.1 Introduction
    • A.2.2 Module stress/error history unit
    • A.2.3 Module revision history unit
    • A.2.4 Module federal stock number unit
    • A.2.5 Module usage/location unit
  • A.3 Alternate access unit
  • • A.3.1 Introduction
    • A.3.2 Alternate access unit (AAU) framework
  • A.4 Input/output units
  • A.5 Power fail imminent (PFI) CSRs
  • • A.5.1 Introduction
    • A.5.2 PFI CSR
    • A.5.3 Power source CSR
• Annex B Modular open architecture overview
• • B.1 Introduction
  • • B.1.1 Modular open architectures
    • B.1.2 Interoperability of modules
    • B.1.3 Adoption of commercial standards
  • B.2 Overview of backplane interconnects
  • • B.2.1 System architectures
    • B.2.2 Interconnect descriptions
  • B.3 Backplane construction
  • • B.3.1 Interconnect mechanisms to provide flexibility in slot usage
    • B.3.2 Customization of the backplane
  • B.4 Pin assignments for special classes of modules
  • B.5 Analog/RF modules
  • B.6 Power supplies
  • B.7 Power fail imminent signal
  • B.8 Event logging
  • B.9 Module test and repair diagnostics
  • B.10 Nonintrusive software development/debug support
  • B.11 Shared-memory and message-passing paradigms
  • B.12 Conformance test requirements
• Annex C Current per connector pin guidelines
• • C.1 Current per connector pin issues
  • • C.1.1 Physical integrity considerations
    • C.1.2 Noise and operating voltage considerations
    • C.1.3 Rationale of military profile connector pin ratings
    • C.1.4 Conclusions
• Annex D Example ROM entries for a MIL profile module
• • D.1 Introduction
  • • D.1.1 Bus info block ROM entries
    • D.1.2 Root directory ROM entries
    • D.1.3 Unit directory ROM entries
    • D.1.4 Textual descriptor leaf entries
    • D.1.5 Node unique ID leaf entries
    • D.1.6 Unit locate leaf ROM entries
• Annex E Bibliography

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