IEEE Std 1394-1995 IEEE Standard for a High Performance Serial Bus -Description
Abstract: A high-speed serial bus that integrates well with most IEEE standard 32-bit and 64-bit parallel buses, as well as such nonbus interconnects as the IEEE Std 1596-1992, Scalable Coherent Interface, is specified. It is intended to provide a low-cost interconnect between cards on the same backplane, cards on other backplanes, and external peripherals. This standard follows the IEEE Std 1212-1991 Command and Status Register (CSR) architecture.
Keywords: backplane, bus, computers, high-speed serial bus, interconnect, parallel buses
Content
1. Overview
1.1 Scope
1.2 References
1.3 Document organization
1.4 Serial Bus applications
1.4.1 Alternate bus
1.4.2 Low-cost peripheral bus
1.4.3 Bus bridge
1.5 Service model
1.6 Document notation
1.6.1 Mechanical notation
1.6.2 Signal naming
1.6.3 Size notation
1.6.4 Numerical values
1.6.5 Packet formats
1.6.6 Register formats
1.6.7 C++ code notation
1.6.8 State machine notation
1.6.9 CSR, ROM, and field notation
1.6.10 Register specification format
1.6.11 Reserved registers and fields
1.6.12 Operation description priorities
1.7 Compliance
1.7.1 CSR Architecture compliance
1.7.2 Serial Bus physical layers
2. Definitions and abbreviations
2.1 Conformance glossary
2.2 Technical glossary
3. Summary description
3.1 Node and module architectures
3.2 Topology
3.2.1 Cable environment
3.2.2 Backplane environment
3.3 Addressing
3.4 Protocol architecture
3.4.1 Data transfer services
3.5 Transaction layer
3.5.1 Transaction layer services
3.5.2 Lock subcommands
3.5.3 Subaction queue independence
3.6 Link layer
3.6.1 Link layer services
3.6.2 Link and transaction layer interactions
3.6.3 Asynchronous arbitration
3.6.4 Isochronous arbitration
3.7 Physical layer
3.7.1 Data bit transmission and reception
3.7.2 Fair arbitration
3.7.3 Cable physical layer
3.7.4 Backplane physical layer
3.8 Bus management
4. Cable PHYspecification
4.1 Cable PHY services
4.1.1 Cable PHY bus management services for the management layer
4.1.2 PHY layer arbitration services for the link layer
4.1.3 PHY layer data services for the link layer
4.2 Cable physical connection specification
4.2.1 Media attachment
4.2.2 Media signal interface
4.2.3 Media signal timing
4.3 Cable PHY facilities
4.3.1 Coding
4.3.2 Cable PHY signals
4.3.3 Cable PHY line states
4.3.4 Cable PHY packets
4.3.5 Cable PHY timing constants
4.3.6 Gap timing
4.3.7 Cable PHY node constants
4.3.8 Node variables
4.3.9 Port variables
4.4 Cable PHY operation
4.4.1 Data transmission and reception
4.4.2 Cable environment arbitration
5. Backplane PHY specification
5.1 Backplane PHY services
5.1.1 Backplane PHY bus management services for the management layer
5.1.2 PHY layer arbitration services for the link layer
5.1.3 PHY layer data services for the link layer
5.2 Backplane physical connection specification
5.2.1 Media attachment
5.2.2 Media signal interface
5.2.3 Media signal timing
5.2.4 Backplane PHY timing
5.3 Backplane PHY facilities
5.3.1 Coding
5.3.2 Backplane PHY signals
5.3.3 Gap timing
5.3.4 Arbitration sequence
5.4 Backplane PHY operation
5.4.1 Arbitration
5.4.2 Backplane environment packet transmission and reception
5.5 Backplane initialization and reset
5.5.1 Backplane PHY reset
5.5.2 Backplane PHY initialization
6. Link layer specification
6.1 Link layer services
6.1.1 Link layer bus management services for the node controller
6.1.2 Link layer asynchronous data services for the transaction layer
6.1.3 Link layer isochronous data services for application layers
6.2 Link layer facilities
6.2.1 Primary packets
6.2.2 Asynchronous packets
6.2.3 Isochronous packets
6.2.4 Primary packet components
6.2.5 Acknowledge packets
6.3 Link layer operation
6.3.1 Overview of link layer operation
6.3.2 Cycle synch event
6.3.3 Details of link layer operation
6.4 Link layer reference code
7. Transaction layer specification
7.1 Transaction layer services
7.1.1 Transaction layer bus management services for Serial Bus management
7.1.2 Transaction layer data services for applications and bus management
7.2 Transaction facilities
7.2.1 Split transaction timer
7.2.2 Transaction retry limit
7.3 Transaction operation
7.3.1 Overview of transaction layer operations
7.3.2 Transaction completion definitions
7.3.3 Details of transaction layer operation
7.3.4 Transaction types
7.3.5 Retry protocols
7.4 CSR Architecture transactions mapped to Serial Bus
