IEEE Std 1355-1995 IEEE Standard for Heterogeneous InterConnect (HIC) (Low-Cost, Low-Latency Scalable Serial Interconnect for Parallel System Construction) -Description

Abstract: Enabling the construction of high-performance, scalable, modular, parallel systems with low system integration cost is discussed. Complementary use of physical connectors and cables, electrical properties, and logical protocols for point-to-point serial scalable interconnect, operating at speeds of 10–200 Mb/s and at 1 Gb/s in copper and optic technologies, is described.

Keywords: flow control, encoding schemes, OMI/HIC, packet routing, parallelism, point-to-point serial scalable interconnect, protocols, routing fabric, serial links, serialization, silicon integration, switch chip, transaction layer, wormhole routing

Content

• 1. Overview
• • 1.1 Scope
  • 1.2 Purpose
• 2. References
• 3. Definitions
• 4. Physical media and logical layers
• • 4.1 Physical media
  • 4.2 Logical layers
  • • 4.2.1 Layer 0: signal layer
    • 4.2.2 Layer 1: character layer
    • 4.2.3 Layer 2: exchange layer
    • 4.2.4 Layer 3: packet layer
    • 4.2.5 Layer 4: transaction layer
  • 4.3 Interaction of layers
  • • 4.3.1 “Downward going”
    • 4.3.2 “Upward Going”
  • 4.4 Implementations defined in the standard
• 5. DS-SE and DS-DE
• • 5.1 General
  • 5.2 DS-SE: physical medium
  • • 5.2.1 Transmission line requirements
  • 5.3 DS-SE signal level
  • • 5.3.1 General
    • 5.3.2 DS-SE link driver
    • 5.3.3 DS-SE link receiver
    • 5.3.4 DS-SE link timing
    • 5.3.5 DS-SE link signals
  • 5.4 DS-DE: physical medium
  • • 5.4.1 Link cable
    • 5.4.2 Connector
    • 5.4.3 Environmental constraints
    • 5.4.4 Optional power supply to DS-DE cable
  • 5.5 DS-DE signal level
  • • 5.5.1 General
    • 5.5.2 DS-DE signals
    • 5.5.3 DS-DE_attenuation budget
    • 5.5.4 DS-DE skew budget
    • 5.5.5 DS-DE link timing
    • 5.5.6 EM Susceptibility
  • 5.6 DS-SE and DS-DE character level
  • 5.7 DS-SE and DS-DE exchange level
  • • 5.7.1 General
    • 5.7.2 DS-SE and DS-DE initialization
    • 5.7.3 Flow control
    • 5.7.4 DS-SE and DS-DE error detection
• 6. TS-FO-02 fiber optic link
• • 6.1 Physical medium
  • • 6.1.1 General optical characteristics
    • 6.1.2 Optical connector
    • 6.1.3 Environmental constraints
  • 6.2 Signal level
  • • 6.2.1 Transmitter and receiver characteristics
    • 6.2.2 TS-FO link timing
    • 6.2.3 TS-FO reference link
    • 6.2.4 Link performance
    • 6.2.5 Eye safety
  • 6.3 TS-FO character level
  • • 6.3.1 General
    • 6.3.2 Symbols
    • 6.3.3 Data characters
    • 6.3.4 Control characters
  • 6.4 TS-FO exchange level
  • • 6.4.1 General
    • 6.4.2 Initialization
    • 6.4.3 Flow control
    • 6.4.4 Error detection
• 7. HS-SE-10
• • 7.1 HS-SE physical medium
  • • 7.1.1 General electrical characteristics
    • 7.1.2 Printed circuit board (PCB)
    • 7.1.3 Single minicoaxial cable
    • 7.1.4 Link cable
    • 7.1.5 Link connectors
    • 7.1.6 Environmental constraints
  • 7.2 HS-SE signal level
  • • 7.2.1 General
    • 7.2.2 Attenuation budget
    • 7.2.3 Line signal levels—driver side
    • 7.2.4 AC coupling of the link
    • 7.2.5 Receiver electrical
    • 7.2.6 EM susceptibility
  • 7.3 HS character level (8B/12B code)
  • • 7.3.1 General
    • 7.3.2 Transmission characters
    • 7.3.3 DC balance
    • 7.3.4 Control characters
    • 7.3.5 The code
  • 7.4 HS exchange level
  • • 7.4.1 General
    • 7.4.2 Start-up
    • 7.4.3 Errors on start-up
    • 7.4.4 Functional
    • 7.4.5 Link reset mechanism
    • 7.4.6 Errors when functional
    • 7.4.7 Shutdown
• 8. HS-FO-10 fiber optic link
• • 8.1 Physical medium
  • • 8.1.1 General optical characteristics
    • 8.1.2 Optical connector
    • 8.1.3 Environmental constraints
  • 8.2 Signal level
  • • 8.2.1 General
    • 8.2.2 Transmitter and receiver characteristics
    • 8.2.3 HS-FO reference link
    • 8.2.4 Link performance
    • 8.2.5 Eye safety
  • 8.3 Character level end exchange level
• 9. Common packet level
• • 9.1 General discussion
  • 9.2 Packet format
  • • 9.2.1 Destination
    • 9.2.2 Payload
    • 9.2.3 End_of_packet marker
  • 9.3 Networks and routing
  • 9.4 Error detection, recovery, and reporting
• 10. Conformance criteria
• • 10.1 Conformance statements
  • 10.2 Definition of subsets
  • 10.3 Conformance statements and cable markings
• Annex A DS-DE connector specification
• • A.1 General
  • A.1 Specification
• Annex B HS-SE connector specification
• • B.1 General
  • B.2 Specification
  • B.3 Shielding
  • B.1 Coaxial contacts
• Annex C TS-FO and HS-FO connector specifications
• • C.1 General
  • C.2 TS-FO and HS-FO multimode connector
  • C.3 HS-FO single-mode connector
  • C.4 TS-FO/HS-FO multimode and HS-FO single-mode connector dimensions
  • C.1 Color coding of connector
• Annex D Rationale
• • D.1 Need for a new standard
  • D.2 Aspects of a parallel systems interconnect
  • • D.2.1 Parallel interconnect
    • D.2.2 Routing
    • D.2.3 Wormhole routing
    • D.2.4 Flow control
  • D.3 Comparison with other types
  • • D.3.1 Telecommunications systems
    • D.3.2 Local area networks
    • D.3.3 Parallel systems interconnect
• Annex E Switch chips, switches, and fabrics
• Annex F Use of the transaction layer—Asynchronous transfer mode (ATM) example
• • F.1 Mapping for ATM
  • • F.1.1 Introduction
    • F.1.2 ATM networks
    • F.1.3 ATM services
    • F.1.4 The ATM protocol stack
    • F.1.5 Virtual channels and virtual paths
    • F.1.6 Mappings for ATM applications interfaces and switch implementations
  • F.2 Bibliography
• Annex G Error handling
• Annex H Flow control calculations
• Annex I Synchronized channel communications
• • I.1 Introduction
  • I.2 Synchronized communication
  • • I.2.1 Channel communication
  • I.3 Virtual channels
  • • I.3.1 Division of messages into packets
    • I.3.2 Packet formats
    • I.3.3 Virtual links
  • I.4 Protocol
  • • I.4.1 Message transmission
    • I.4.2 Message reception
  • I.5 Notes
• Annex J Example DS-SE driver circuit
• Annex K DS-DE optional power supply recommendation
• • K.1 General
  • K.2 Example components
  • K.3 EMC
• Annex L DS-DE fixed connector PCB recommendation
• Annex M DS-DE cable (10 core) recommendation
• Annex N DS-DE multiway connector housing recommendation
• Annex O HS-SE fixed connector PCB recommendation
• Annex P HS-SE cable recommendation
• Annex Q HS-SE connector multiway housing recommendation
• Annex R TS/HS-FO connector PCB and front panel cut-out recommendation
• Annex S TS/HS-FO fiber cable recommendation

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