ISO/IEC 13213 : 1994 [ANSI/IEEE Std 1212, 1994 Edition] (Incorporates ANS/IEEE Std 1212-1991) Information technology— Microprocessor systems—Control and Status Registers (CSR) Architecture for microcomputer buses -Description

Content

• 1. Document structure and notation
• • 1.1 Document structure
  • 1.2 References
  • 1.3 Conformance levels
  • 1.4 Technical glossary
  • 1.5 Bit, byte, and quadlet ordering
  • 1.6 Numerical values
  • 1.7 C code notation
  • 1.8 CSR, ROM, and field notation
  • 1.9 Register specification format
  • 1.10 Reserved registers and fields
• 2. Objectives and scope
• • 2.1 Scope
  • 2.2 Objectives
• 3. Transaction set requirements
• • 3.1 Transaction overview
  • 3.2 Read and write transactions
  • 3.3 Noncoherent lock transactions
  • 3.4 Transaction errors
  • 3.5 Immediate effects
• 4. Node addressing
• • 4.1 Node addresses
  • 4.2 Extended addressing
  • 4.3 64-bit fixed addressing
  • 4.4 Private addresses
  • 4.5 Initial node space
  • 4.6 Extended address spaces
  • 4.7 Indirect space
  • 4.8 Address space offsets
• 5. Node architectures
• • 5.1 Modules, nodes, and units
  • 5.2 Node states
  • 5.3 Node testing
  • • 5.3.1 Access-path tests
    • 5.3.2 Reset test
    • 5.3.3 Diagnostic tests
    • 5.3.4 Non-standard diagnostic tests
  • 5.4 Multinode modules
  • 5.5 On-line replacement (OLR)
• 6. Unit architectures
• • 6.1 Unit architecture overview
  • 6.2 Interrupts
  • • 6.2.1 Interrupt-target registers
    • 6.2.2 Interrupt-poll registers
  • 6.3 Message passing
  • 6.4 Globally synchronized clocks
  • • 6.4.1 Clock overview
    • 6.4.2 Clock synchronization
    • 6.4.3 Clock update models
    • 6.4.4 Updating clock registers
    • 6.4.5 Clock accuracy requirements
  • 6.5 Memory unit architectures
  • 6.6 Unit architecture environment
• 7. CSR definitions
• • 7.1 Register names and offsets
  • 7.2 Minimal implementations
  • 7.3 Unsupported register accesses
  • 7.4 Register definitions
  • • 7.4.1 STATE_CLEAR
    • 7.4.2 STATE_SET
    • 7.4.3 NODE_IDS
    • 7.4.4 RESET_START
    • 7.4.5 INDIRECT_ADDRESS
    • 7.4.6 INDIRECT_DATA
    • 7.4.7 SPLIT_TIMEOUT
    • 7.4.8 ARGUMENT
    • 7.4.9 TEST_START
    • 7.4.10 TEST_STATUS
    • 7.4.11 UNITS_BASE
    • 7.4.12 UNITS_BOUND
    • 7.4.13 MEMORY_BASE
    • 7.4.14 MEMORY_BOUND
    • 7.4.15 INTERRUPT_TARGET
    • 7.4.16 INTERRUPT_MASK
    • 7.4.17 CLOCK_VALUE
    • 7.4.18 CLOCK_TICK_PERIOD
    • 7.4.19 CLOCK_STROBE_ARRI VED
    • 7.4.20 CLOCK_STROBE_INFO
    • 7.4.21 Message targets
    • 7.4.22 ERROR_LOG registers
• 8. ROM specification
• • 8.1 Introduction
  • • 8.1.1 ROM design assumptions
    • 8.1.2 ROM formats
    • 8.1.3 Driver and diagnostic identifiers
    • 8.1.4 ASCII text
    • 8.1.5 CRC calculations
  • 8.2 ROM formats
  • • 8.2.1 First ROM quadlet
    • 8.2.2 Minimal ROM format
    • 8.2.3 General ROM format
    • 8.2.4 Directory formats
    • 8.2.5 Leaf format
    • 8.2.6 Textual_descriptor
  • 8.3 bus_info_block
  • 8.4 Root directory entries
  • • 8.4.1 Bus_Dependent_Info
    • 8.4.2 Module_Vendor_ld
    • 8.4.3 Module_Hw_Version
    • 8.4.4 Module_Spec_ld
    • 8.4.5 Module_Sw_Version
    • 8.4.6 Module_Dependent_Info
    • 8.4.7 Node_Vendor_ld
    • 8.4.8 Node_Hw_Version
    • 8.4.9 Node_Spec_Id
    • 8.4.10 Node_Sw_Version
    • 8.4.11 Node_Capabilities
    • 8.4.12 Node_Unique_Id
    • 8.4.13 Node_Units_Extent
    • 8.4.14 Node_Memory_Extent
    • 8.4.15 Node_Dependent_Info
    • 8.4.16 Unit_Directory
  • 8.5 Unit directories
  • • 8.5.1 Unit_Spec_Id
    • 8.5.2 Unit_Sw_Version
    • 8.5.3 Unit_Dependent_Info
    • 8.5.4 Unit_Location
    • 8.5.5 Unit_Poll_Mask
  • 8.6 Key definitions
  • 8.7 company_ids
  • • 8.7.1 company_id assignments
    • 8.7.2 company_id mappings
• 9. Bus standard requirements
• Annex A Bibliography
• Annex B Bus topologies
• • B.1 Specialized buses
  • • B.1.1 Multiple-bus topologies
    • B.1.2 Dual-port nodes
  • B.2 Fault retry protocols
  • • B.2.1 Hardware fault recovery
    • B.2.2 Software fault recovery
• Annex C System initialization
• • C.1 System initialization summery
  • C.2 Node address assignments
  • C.3 Processor-cache model
  • C.4 Address protection
  • C.5 Power distribution models
• Annex D Bus transactions
• • D.1 Transaction overview
  • D.2 Transaction components
  • D.3 Request subaction fields
  • D.4 Response subaction fields
• Annex E Bus bridges
• • E.1 Address-invariant mappings
  • E.2 Transaction forwarding
  • E.3 Transaction ordering
  • • E.3.1 Split-response transaction ordering
    • E.3.2 Buffered-write transparency
    • E.3.3 Weakly ordered move transactions
    • E.3.4 Queue-dependency deadlocks
  • E.4 Address domains
  • E.5 Protection boundaries
  • E.6 Coherence domains

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