IEEE Std 1284-2000 IEEE Standard Signaling Method for a Bidirectional Parallel Peripheral Interface for Personal Computers -Description

Abstract: A signaling method for asynchronous, fully interlocked, bidirectional parallel communications between hosts and printers or other peripherals is defined. A functional subset of the signaling method may be implemented on personal computers (PCs) or equivalent parallel port hardware with new software. New electrical interfaces, cabling, and interface hardware that provides improved performance while retaining backward compatibility with this subset is detailed.

Keywords: bidirectional parallel communications, computers, interfaces, PCs, personal computers, printers

Content

• 1. Overview
• • 1.1 Scope
  • 1.2 Purpose
• 2. References
• 3. Definitions
• • 3.1 General terminology
  • 3.2 Communication modes
  • 3.3 Operating phases
  • • 3.3.1 Compatibility Mode phases
    • 3.3.2 Nibble and Byte Mode phases
    • 3.3.3 ECP Mode phases
    • 3.3.4 EPP mode phases
    • 3.3.5 Additional phases
• 4. Features and compliance
• • 4.1 Interface overview
  • 4.2 Features
  • 4.3 Device compatibility criteria
  • 4.4 Device compliance criteria
  • • 4.4.1 Mechanical
    • 4.4.2 Electrical
    • 4.4.3 Protocol
  • 4.5 Cable compliance criteria
• 5. Interface signals
• • 5.1 HostClk/nWrite (nStrobe): host driven
  • 5.2 AD1…AD8 (Data1…Data8)
  • 5.3 PtrClk/PeriphClk/Intr (nAck): peripheral driven
  • 5.4 PtrBusy/PeriphAck/nWait (busy): peripheral driven
  • 5.5 AckDataReq/nAckReverse (PError): peripheral driven
  • 5.6 Xflag (Select): peripheral driven
  • 5.7 HostBusy/HostAck/nDStrb (nAutoFd): host driven
  • 5.8 Peripheral Logic High: peripheral driven
  • 5.9 nReverseRequest (nInit): host driven
  • 5.10 nDataAvail/nPeriphRequest (nFault): peripheral driven
  • 5.11 1284 Active/nAStrb (nSelectIn): host driven
  • 5.12 Host Logic High: host driven
• 6. Interface concepts
• • 6.1 Link level and data level separation
  • 6.2 IEEE 1284 communication options
  • 6.3 Nibble Mode/Byte Mode transfer
  • 6.4 Host-initiated transfers
  • 6.5 Peripheral-initiated transfers
  • 6.6 Multiple byte transfers
  • 6.7 Interface errors
  • 6.8 Peripheral error resolution
  • 6.9 ECP Mode command/data
  • • 6.9.1 ECP Mode data compression
    • 6.9.2 ECP Mode channel addressing
  • 6.10 EPP Mode addressing
  • 6.11 Device identification
• 7. Interface operation
• • 7.1 Power-On
  • 7.2 Initialization
  • 7.3 Compatibility Mode
  • 7.4 Negotiation
  • • 7.4.1 Successful negotiation
    • 7.4.2 Unsuccessful negotiation
  • 7.5 Peripheral-to-host transfer modes
  • • 7.5.1 Nibble Mode
    • 7.5.2 Byte mode
    • 7.5.3 ECP Mode
    • 7.5.4 EPP Mode
  • 7.6 Device ID
  • 7.7 Termination
  • • 7.7.1 Valid state termination
    • 7.7.2 Immediate termination
  • 7.8 Collisions
• 8. Mechanical and electrical interface
• • 8.1 General considerations
  • 8.2 Mechanical characteristics
  • • 8.2.1 Connectors
    • 8.2.2 Connector pin assignments
    • 8.2.3 Cable interconnections
  • 8.3 Electrical characteristics
  • • 8.3.1 IEEE Std 1284-2000 compliant cable
    • 8.3.2 Level 1 device
    • 8.3.3 Level 2 device
    • 8.3.4 Level 2 example
    • 8.3.5 Power-off state of the interface
    • 8.3.6 Environmental specifications
• 9. Software support
• • 9.1 General considerations
  • 9.2 Application level compatibility
  • 9.3 MS-DOS IEEE 1284 driver
  • 9.4 Windows 1284 driver
  • 9.5 Reverse channel data
  • 9.6 Link performance
• Annex A Timing specifications
• Annex B Signal transition events
• Annex C Centronics and PC-compatible parallel interfaces
• • C.1 Overview
  • C.2 Centronics interface background information
  • C.3 Classic Centronics Standard Parallel Interface
  • • C.3.1 Interface connector and pin assignments
    • C.3.2 Signal definitions
    • C.3.3 Electrical specifications
    • C.3.4 Interface timing
  • C.4 PC Parallel and PC-Compatible Printer Interfaces
  • • C.4.1 Interface connectors and pin assignments
    • C.4.2 Signal definitions
    • C.4.3 Electrical specifications
    • C.4.4 Interface timing
  • C.5 Enhanced and bidirectional parallel printer interface
  • • C.5.1 Interface connectors and pin assignments
    • C.5.2 Signal definitions
    • C.5.3 Electrical specifications
    • C.5.4 Interface timing
  • C.6 Printer interface variations
  • • C.6.1 Strobe-to-Busy timing variations
    • C.6.2 Busy-to-Ack Timing Variations
• Annex D Bibliography
• Annex E Reducing data loss in ECP reverse termination

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