IEEE Std 1212.1-1993 IEEE Standard for Communicating Among Processors and Peripherals Using Shared Memory (Direct Memory Access—DMA) -Description
Abstract: Primitive yet high-performance means are defined for passing messages across the bus between the Processor and some form of intelligence in the I/O Unit's Function. This message-passing scheme makes minimal demands on the instruction set and hardware required. In addition, several simple conventions are defined for the structure of the messages passed. The intent is to provide a standard architectural framework that supports the detailed definition of application-dependent I/O Unit and Function interface standards. The algorithms and definitions themselves are useful in the design of integrated circuits for I/O.
Keywords: direct memory access, DMA, memory, I/O, processor
Content
1. Overview
1.1 Scope of DMA recommendations
1.2 Objectives
1.3 Overview of DMA
1.3.1 Bus topologies considered
1.3.2 I/O transaction flow and use of memory
1.3.3 Node and queue topology
1.3.4 Message priority handling
2. References
3. Document structure and notation
3.1 Document structure and conformance requirements
3.2 Conformance levels
3.3 Technical glossary
3.4 Data structure notation
3.4.1 Address-invariant (DMA) notation
3.4.2 Big endian notation
3.4.3 Little endian notation
3.5 Node description (capitalization)
3.6 Notation used for algorithms
3.6.1 Notation for variables
3.6.2 Notation for bus interface access
3.6.3 Special macros and functions
4. Background concepts
4.1 Miscellaneous components
4.1.1 Expected interrupt mechanisms
4.1.2 Methods of flow control
4.1.3 Software access to bus transactions
4.2 Circular Queue
4.3 Dispatch List
4.4 Shareable List
4.5 Mailbox
4.6 Hybrid DMA schemes
4.6.1 Circular Queues outbound, Mailbox inbound
4.6.2 Mailbox agents as message scheme converters
4.6.3 Shareable List agents as message scheme converters
4.7 Device-to-Device DMA
4.7.1 General description of Device-to-Device DMA
4.7.2 Device-to-Device data structure use
4.7.3 Bus transaction-ordering considerations
4.7.4 Driver considerations
5. Specification of Circular Queues as a DMA interface
5.1 Overall description of Circular Queue DMA applied to I/O
5.2 Circular Queue data structures
5.3 Specific services Circular Queues require from underlying bus system
5.4 Unit initialization steps for Circular Queues
5.5 Circular Queue enqueue operations
5.6 Circular Queue dequeue operations
6. Specification of Dispatch Lists as a DMA interface
6.1 Overall description of Dispatch List DMA applied to I/O
6.2 Dispatch List data structures
6.3 Specific services Dispatch Lists require from underlying bus system
6.4 Unit initialization steps for Dispatch lists
6.5 Dispatch list enqueue operation
6.6 Dispatch List dequeue operations
7. Specification of Shareable Lists as a DMA interface
7.1 Overall description of Shareable List DMA applied to I/O
7.2 Shareable List data structures
7.3 Specific services Shareable Lists require from underlying bus system
7.4 Unit initialization steps for Shareable Lists
7.5 Shareable List enqueue operations
7.6 Shareable List dequeue operations
8. Specification of Mailboxes as a DMA interface
8.1 Overall description of Mailbox DMA applied to I/O
8.2 Mailbox data structures
8.3 Specific services Mailbox DMA requires from underlying bus system
8.4 Unit initialization steps for Mailbox DMA
8.5 Mailbox enqueue operations
8.6 Mailbox dequeue operations
9. Specification of Device-to-Device DMA
9.1 Device-to-Device DMA data structures
9.2 Specific services required from the underlying bus system
9.3 Unit initialization steps for Device-to-Device DMA
9.4 Producer I/O Unit enqueue operations for Device-to-Device DMA
9.5 Consumer I/O Unit operations for Device-to-Device DMA
9.6 Producer unit operations for buffer return
9.7 Producer unit operations for terminating Device-to-Device DMA
10. Specifications and conventions for DMA message structure
10.1 Overview of message structure
10.2 DMA message specifications
10.2.1 Rules of DMA memory ownership
10.2.2 Demultiplexing of messages in shared queues
10.2.3 Block vector structures for passing segmented data
10.3 Guidelines for DMA message conventions
10.3.1 Overall message conventions
10.3.2 Transaction-initiation message formats
10.3.3 Transaction-completion message formats
10.3.4 Effect of available message sizes
11. Details: Specifications applying to all models
11.1 Services assumed from the underlying bus system
11.1.1 Expected bus transactions
11.1.2 Bus transaction usage
11.1.3 Transaction forwarding through bridges
11.2 DMA Controller functions
11.2.1 Required primitive facilities
11.2.2 First optional enhancement: Traversing block vectors
11.2.3 Final option: Full DMA message support
11.3 Initialization, powerfail recovery, and reset
11.3.1 Unit_control CSR
11.3.2 Unit_status CSR
11.3.3 Initialization CSRs
11.3.4 General unit initialization steps
11.4 Interrupt mechanisms
11.5 Other specifications applying to all models
Annex A Example applications
A.1 Use of building blocks to build an interface
A.2 Examples of queue use to build an Ethernet interface
A.2.1 Ethernet example #1: Two “outbound” queues—Simple data movement
A.2.2 Ethernet example #2: Two queues—Disk-like interface
A.2.3 Ethernet example #3: Three queues—Separate receive buffer pool
A.2.4 Ethernet example #4: Four queues: Separate send/receive channels
A.3 An example disk interface (detailed) using Circular Queues
A.3.1 Unit-global data structures
A.3.2 Outbound message use
A.3.3 Inbound message use
A.3.4 Powerfail recovery and unit reset
Annex B Caching issues
Annex C Notes on I/O Unit Design
C.1 Overall I/O node model
C.2 Frontplane and application control
Annex D Coarse performance comparisons and tradeoffs
D.1 Coarse analysis of bus traffic for DMA models
D.2 Coarse analysis of software overhead for DMA models
D.2.1 Processor interrupt overhead
D.2.2 I/O Unit block-copy set-up overhead
D.3 Rough topological comparisons
D.3.1 Suitability for large numbers of messages
D.3.2 Suitability for large numbers of units—multiple producers
D.3.3 Suitability for Processor-to-Processor communication
D.3.4 Cost of memory use
D.3.5 Cost of special hardware
D.3.6 Reliability
Annex E Description of former Circular Queue options
E.1 Optional, multi-segment extension of a Circular Queue
