IEEE Std 1212™-2001 IEEE Standard for a Control and Status Registers (CSR) Architecture for Microcomputer Buses -Description

Abstract: A common bus architecture (which includes functional components—modules, nodes, and units—and their address space, transaction set, CSRs, and configuration information) suitable for both parallel and serial buses is provided in this standard. Bus bridges are enabled by the architecture, but their details are beyond its scope. Configuration information is self-administered by vendors and organizations based upon IEEE Registration Authority company_id.

Keywords: address space, architecture, bus, computer, CSR, interconnect, microprocessor, register, transaction set

Content

• 1. Overview
• • 1.1 Scope
  • 1.2 Purpose
• 2. References
• 3. Definitions and notation
• • 3.1 Definitions
  • • 3.1.1 Conformance
    • 3.1.2 Technical glossary
    • 3.1.3 Abbreviations
  • 3.2 Notation
  • • 3.2.1 Numeric values
    • 3.2.2 Bit, byte, and quadlet ordering
• 4. Architectural framework
• • 4.1 Modules, nodes, and units
  • 4.2 Addressing
• 5. Transaction set
• • 5.1 Read and write transactions
  • 5.2 Lock transactions
  • 5.3 Bus-dependent transactions
  • 5.4 Split transactions
  • 5.5 Completion status
• 6. CSR definitions
• • 6.1 STATE_CLEAR / STATE_SET registers
  • 6.2 NODE_IDS register
  • 6.3 RESET_START register
  • 6.4 SPLIT_TIMEOUT register
  • 6.5 MESSAGE_REQUEST / MESSAGE_RESPONSE registers
• 7. Configuration ROM
• • 7.1 IEEE Registration Authority
  • 7.2 ROM formats
  • 7.3 CRC calculation
  • 7.4 Minimal ASCII
  • 7.5 Data structures
  • • 7.5.1 Directory format
    • 7.5.2 Extended key format
    • 7.5.3 Leaf format
    • 7.5.4 Descriptors
  • 7.6 Required and optional usage
  • • 7.6.1 Root directory
    • 7.6.2 Instance directories
    • 7.6.3 Unit directories
    • 7.6.4 Feature directories
    • 7.6.5 Keyword leaves
  • 7.7 Directory entries
  • • 7.7.1 Bus_Dependent_Info entry
    • 7.7.2 Vendor_ID entry
    • 7.7.3 Vendor_Info entry
    • 7.7.4 Hardware_Version entry
    • 7.7.5 Module_Primary_EUI_64
    • 7.7.6 Module_Info
    • 7.7.7 Node_Capabilities entry
    • 7.7.8 EUI_64 entry
    • 7.7.9 Unit_Directory entry
    • 7.7.10 Specifier_ID entry
    • 7.7.11 Version entry
    • 7.7.12 Dependent_Info entry
    • 7.7.13 Unit_Location entry
    • 7.7.14 Model_ID entry
    • 7.7.15 Instance directory entry
    • 7.7.16 Keyword_Leaf entry
    • 7.7.17 Feature_Directory entry
    • 7.7.18 Extended_ROM entry
    • 7.7.19 Directory_ID entry
    • 7.7.20 Revision entry
• Annex A Configuration ROM examples
• • A.1 Bus information block and root directory
  • A.2 Single instance with a single unit architecture
  • A.3 Single instance with multiple unit architectures
  • A.4 Multiple instances with identical unit architectures
  • A.5 Extended keys
• Annex B Keyword examples
• Annex C Bibliography

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