ISO/IEC 10861 : 1994 [ANSI/IEEE Std 1296, 1994 Edition] Information technology—Microprocessor systems— High-performance synchronous 32-bit bus: MULTIBUS II -Description

Content

• 1. General overview
• • 1.1 Scope
  • 1.2 Normative references
• 2. Definitions
• 3. Guide to notation
• • 3.1 General
  • 3.2 Signal notation
  • 3.3 Figure notation
  • 3.4 Notation in state-flow diagrams
  • 3.5 Notation for multiple bit data representation
• 4. PSB overview
• • 4.1 General
  • 4.2 Address/data path and system control signals
  • 4.3 Message-passing facility
  • 4.4 Interconnect facility
  • 4.5 Synchronous operation of the PSB
  • 4.6 Bus operations on the PSB
  • • 4.6.1 Arbitration operation
    • 4.6.2 Transfer operation
    • 4.6.3 Exception operation
  • 4.7 Central services module
• 5. Signal descriptions
• • 5.1 General
  • 5.2 Signal groups
  • • 5.2.1 Arbitration operation signal group
    • 5.2.2 Address/data bus signal group
    • 5.2.3 System control signal group
    • 5.2.4 Exception operation signal group
    • 5.2.5 Central control signal group
    • 5.2.6 Power
• 6. PSB protocol
• • 6.1 General
  • 6.2 Arbitration operation
  • • 6.2.1 Agent arbitration ID and cardslot ID assignment
    • 6.2.2 Bus arbitration priority
    • 6.2.3 Bus ownership
    • 6.2.4 Parking and bus release
    • 6.2.5 Arbitration priority example
    • 6.2.6 Resolution algorithm example
  • 6.3 Transfer operation
  • • 6.3.1 Types of transfer operation
    • 6.3.2 Transfer operation lock
    • 6.3.3 Agent status
    • 6.3.4 Address space definitions in transfer operations
    • 6.3.5 Data width during transfer operations
    • 6.3.6 Transfer-width error reporting during transfer operations
    • 6.3.7 Data alignment interface example
  • 6.4 Exception operation
  • • 6.4.1 Causes of exception operations
    • 6.4.2 Priority of errors
  • 6.5 Central control functions
  • • 6.5.1 Clock source
    • 6.5.2 System level resets
    • 6.5.3 Arbitration ID and cardslot ID assignment
    • 6.5.4 Time-out monitoring
  • 6.6 State-flow diagrams
  • • 6.6.1 State-flow sequence for an agent monitoring the bus
    • 6.6.2 State-flow sequence for an arbitration operation
    • 6.6.3 State-flow sequence for bus owners in a transfer operation
    • 6.6.4 State-flow diagram for replying agents in a transfer operation
    • 6.6.5 Effects of exception operations on state-flow diagrams
• 7. Electrical characteristics
• • 7.1 General
  • 7.2 AC timing specifications
  • 7.3 DC specifications for signals
  • 7.4 Current limitations per connector
  • 7.5 Pin assignments
  • • 7.5.1 PSB pin assignments
    • 7.5.2 P2 recommended power pin assignments
• 8. Mechanical specifications
• • 8.1 General
  • 8.2 Board sizes and dimensions
  • 8.3 Printed board layout considerations
  • 8.4 Front panel
  • 8.5 Connectors
  • 8.6 Backplanes
  • • 8.6.1 Mounting
    • 8.6.2 Backplane design
    • 8.6.3 PSB backplane specifications
    • 8.6.4 PSB backplane characteristics
• 9. IEEE 1296 System Interface specification
• • 9.1 Overview
  • • 9.1.1 Scope
    • 9.1.2 Object
    • 9.1.3 Architecture overview
    • 9.1.4 System model
  • 9.2 Interconnect space operation
  • • 9.2.1 Introduction
    • 9.2.2 Interface model
    • 9.2.3 Interconnect address format
    • 9.2.4 Vendor identification registers
    • 9.2.5 Compliant interconnect template structure
    • 9.2.6 Minimum compliant template
  • 9.3 I/O space operation
  • • 9.3.1 Introduction
    • 9.3.2 Interface model
    • 9.3.3 Address assignment rules
  • 9.4 Memory space operations
  • • 9.4.1 Introduction
    • 9.4.2 Interface model
    • 9.4.3 Address assignment rules
  • 9.5 Message space operations
  • • 9.5.1 Introduction
    • 9.5.2 Interface model
    • 9.5.3 Address assignment rules
    • 9.5.4 Message space operation
    • 9.5.5 Message model
    • 9.5.6 Solicited data transfer protocol
    • 9.5.7 Packet formats
• 10. IEEE 1296 capabilities
• • 10.1 Characteristic codes
  • • 10.1.1 Introduction
    • 10.1.2 P2 connector
    • 10.1.3 Form factor
• Annex A Recommended documentation practices
• • A.1 Introduction
  • A.2 Bus owner address space support
  • A.3 Replying agent address space support
  • A.4 Data path
  • A.5 Message support
  • A.6 CSM support
  • A.7 Sequential transfer support
  • A.8 Power fail support
  • A.9 Interconnect template support
  • A.10 Temperature and airflow assumptions
  • A.11 RSTNC* assertion time
  • A.12 Example of recommended documentation practices

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