ANSI/IEEE 896.1a-1993 ISO/IEC 10857 : 1994 Information technology— Microprocessor systems— Futurebus+ —Logical protocol specification -Description

Abstract: This International Standard provides a set of tools with which to implement a Futurebus+ architecture with performance and cost scalability over time, for multiple generations of single- and multiple-bus multiprocessor systems. Although this specification is principally intended for 64-bit address and data operation, a fully compatible 32-bit subset is provided, along with compatible extensions to support 128- and 256-bit data highways. Allocation of bus bandwidth to competing modules is provided by either a fast centralized arbiter, or a fully distributed, one or two pass, parallel contention arbiter. Bus allocation rules are provided to suit the needs of both real-time (priority based) and fairness (equal opportunity access based) configurations. Transmission of data over the mulitplexed address/data highway is governed by one of two intercompatible transmission methods: a) a technology-independent, compelled-protocol, supporting broadcast, broadcall, and transfer intervention (the minimum requirement for all Futurebus+ systems), and b) a configurable transfer-rate, source-synchronized protocol supporting only block transfers and source-synchronized broadcast for systems requiring the highest possible performance. Futurebus+ takes its name from its goal of being capable of the highest possible transfer rate consistent with the technology available at the time modules are designed, while ensuring compatibility with all modules designed to this standard both before and after. The plus sign (+) refers to the extensible nature of the specification, and the hooks provided to allow further evolution to meet unanticipated needs of specific application architectures. It is intended that this Internation Standard be used as a key component of an approved IEEE Futurebus+ profile.

Keywords: bus architecture, Futurebus+, logical protocol, multiprocessor systems

Content

• 1. Overview
• • 1.1 Scope
  • 1.2 Normative references
• 2. Definitions and structure
• • 2.1 Special word usage
  • 2.2 Definitions
  • 2.3 Signal conventions
  • 2.4 Document structure
  • 2.5 Futurebus+ logo
  • 2.6 Bus line description
  • • 2.6.1 Information lines
    • 2.6.2 Synchronization lines
    • 2.6.3 Distributed arbitration and arbitrated message lines
    • 2.6.4 RE^* reset/bus initialize
    • 2.6.5 Central arbiter
    • 2.6.6 GA[4..0]^* geographical address
  • 2.7 Attribute cross reference
  • 2.8 Implementation mnemonics
• 3. Bus signaling environment
• • 3.1 Description
  • • 3.1.1 Incident wave switching
    • 3.1.2 Skew
  • 3.2 Specification
  • • 3.2.1 Skew
    • 3.2.2 Glitch filters
• 4. Centralized arbitration
• • 4.1 Description
  • • 4.1.1 Bus lines used for centralized arbitration
    • 4.1.2 Centralized arbitration operation
    • 4.1.3 Central arbiter description
  • 4.2 Specification
  • • 4.2.1 Bus arbitration attributes
    • 4.2.2 Bus arbitration signals
• 5. Distributed arbitration and arbitrated messages
• • 5.1 Description
  • • 5.1.1 Arbitrated messages-central arbiter
    • 5.1.2 Arbitration and messages—distributed arbiter
    • 5.1.3 Bus lines
    • 5.1.4 Arbitration competition logic
    • 5.1.5 Arbitration competition settling time
    • 5.1.6 Arbitration states
    • 5.1.7 Arbitration phases
    • 5.1.8 Arbitration examples
  • 5.2 Specification
  • • 5.2.1 Arbitrated message attributes—central arbiter
    • 5.2.2 Arbitrated message attributes—distributed arbiter
    • 5.2.3 Arbitration attributes—distributed arbiter
    • 5.2.4 General arbitration and message attributes
    • 5.2.5 Arbitration timing attributes
    • 5.2.6 Arbitration error attributes
    • 5.2.7 Signal definition
    • 5.2.8 Protocol definition—distributed arbitration and messages
    • 5.2.9 Protocol definition—central arbiter messages
• 6. Parallel protocol
• • 6.1 Description
  • • 6.1.1 Mastership
    • 6.1.2 Transactions
    • 6.1.3 Bus transaction phases
    • 6.1.4 Data transfer protocols
    • 6.1.5 Broadcast handshake
    • 6.1.6 Intervention
    • 6.1.7 Cache line status
    • 6.1.8 Split transactions
    • 6.1.9 Locked transactions
    • 6.1.10 Lock commands
    • 6.1.11 Busy
    • 6.1.12 Wait
    • 6.1.13 Extended bus width
    • 6.1.14 Extended address
    • 6.1.15 Module capabilities
    • 6.1.16 Transactions
    • 6.1.17 Bus signal descriptions
    • 6.1.18 Bus beats
    • 6.1.19 Transaction examples
  • 6.2 Specification
  • • 6.2.1 Attribute definition
    • 6.2.2 Signal definition
    • 6.2.3 Protocol definition
• 7. Bus/system management
• • 7.1 Description
  • • 7.1.1 Bus control
    • 7.1.2 Futurebus+ control and status registers
  • 7.2 Specification
  • • 7.2.1 Bus control attributes
    • 7.2.2 RE(*) reset signal
    • 7.2.3 Protocol definition
    • 7.2.4 Futurebus+ control and status registers
• 8. Cache coherence
• • 8.1 Description
  • • 8.1.1 Cache attributes
    • 8.1.2 Bus snooping
    • 8.1.3 Cache coherence using connected transactions
    • 8.1.4 Cache coherence using split transactions on a single bus segment
    • 8.1.5 Using split transactions to delay invalidation completions
    • 8.1.6 Summary of cache coherence commands and status:
    • 8.1.7 Illegal attribute combinations
  • 8.2 Specification
  • • 8.2.1 Module attributes
    • 8.2.2 Status attributes
    • 8.2.3 Cache module attributes per cache line
    • 8.2.4 Requester attributes per cache line
    • 8.2.5 Responder attributes per cache line
    • 8.2.6 Protocol definition
• 9. Message passing
• • 9.1 Description
  • • 9.1.1 Frame level
    • 9.1.2 Message level
  • 9.2 Specification
  • • 9.2.1 Attribute definition
    • 9.2.2 Frame format specification
    • 9.2.3 Message size
    • 9.2.4 Frame interval
    • 9.2.5 Sequence number
    • 9.2.6 Exception type field
    • 9.2.7 Protocol definition
• Annex A Bibliography

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