IEEE Std 1014.1-1994 IEEE Standard for Futurebus+TM/VME64 Bridge -Description
Abstract: The logical protocal layer for bridging between a Futurebus+ system and a VME64 system in a tightly coupled fashion is defined. Transferring of both data and events is specified. The physical layer is not defined in this standard. Implementers are free to define and use the Bridge in the manner that best fits the application for optimum performance, functionality, and cost trade-offs. The Bridge provides for software transparency such that, at the application level, software is not aware of accesses that reach across a Bridge into the modules of another bus.
Keywords: Bus Bridge, Futurebus+, VMEbus, VME64
Content
1. Overview
1.1 Scope
1.2 Purpose
2. References
3. Definitions
3.1 Special keywords
3.2 Bridge-specific definitions
3.3 Bus-specific definitions
3.4 CSR and ROM definitions
3.4.1 CSR entries
3.4.2 ROM entries
3.4.3 Addressing conventions
3.4.4 Logic conventions
3.4.5 Signal names
3.4.6 Register specification format
4. System model and architecture
4.1 Introduction
4.2 Single bridge model
4.3 Dual Bridge model
4.4 Bridge Interconnect Bus
4.5 Bridge transaction translator
4.6 Reference tables
5. Bridge control and status registers (CSRs)
5.1 Introduction
5.1.1 CSR Architecture standard node registers
5.1.2 Extended addressing
5.1.3 CSR Architecture node registers
5.1.4 Initial node space
5.1.5 Indirect space
5.1.6 Bridge register locations
5.2 CSRs
5.2.1 Summary of Bridge-specific CSRs
5.2.2 CSR Architecture core registers
5.3 ROM window
5.4 CSR specifications
5.4.1 CSR Architecture core
5.4.2 Bus-dependent
5.5 ROM specification
5.5.1 Module-specific characteristics
5.5.2 Data Channel
5.5.3 Event Channel
5.5.4 Dual Port Memory
6. Data Channel
6.1 Description
6.1.1 Futurebus+ to VME64 (F2V) Data Channel
6.1.2 VME64 to Futurebus+ (V2F) Data Channel
6.1.3 Bridge and transaction error handling
6.1.4 Bus request priority
6.1.5 Supporting interlocked operations
6.1.6 F2V retry
6.2 Specification
6.2.1 Common CSRs
6.2.2 F2V Data Channel
6.2.3 V2F Data Channel
6.3 Data Channel ROM specification
6.3.1 F2V Data Channel capabilities
6.3.2 V2F Data Channel capabilities
7. Event Channel
7.1 Description
7.1.1 Futurebus+ to VME64 (F2V) Event Channel
7.1.2 VME64 to Futurebus+ (V2F) Event Channel
7.1.3 Event Channel registers
7.2 Specification
7.2.1 Event Channel interfaces
7.2.2 Event Channel transactions
7.2.3 Event Channel Status register
7.2.4 Event Channel Clear register
7.2.5 FEG registers
7.2.6 VEG registers
7.3 Event Channel ROM specification
8. Dual Port Memory Channel
8.1 Description
8.1.1 Dual Port Memory use
8.1.2 Dual Port Memory registers
8.1.3 Data transaction types
8.1.4 Lock operations
8.1.5 Memory data integrity
8.1.6 System topology considerations
8.2 Specification
8.2.1 Dual Port Memory configuration
8.2.2 Dual Port Memory transactions
8.2.3 Dual Port Memory Control register
8.2.4 Dual Port Memory Status register
8.2.5 Dual Port Memory Futurebus+ base and bound registers
8.2.6 Dual Port Memory Channel Futurebus+ error address register
8.2.7 Dual Port Memory VME64 base and bound registers
8.3 Dual Port Memory Channel ROM specification
8.3.1 Dual Port Memory configuration
8.3.2 Dual Port Memory size implemented
8.3.3 Dual Port Memory VME64 address modifier (AM) codes supported
