ANSI/IEEEANSI/IEEE Std 1014-1987 IEEE Standard for A Versatile Backplane Bus: VMEbus -Description
Abstract: This 1014 standard specifies a high-performance backplane bus for use in
microcomputer systems that employ single or multiple microprocessors. It is
based on the VMEbus specification, released by the VME Manufacturers' Group in
August of 1982. The bus includes four subbuses: data transfer bus, priority
interrupt bus, arbitration bus, and utility bus. The data transfer bus supports
8-, 16-, and 32-bit transfers over a non-multiplexed 32-bit data and address
highway. The transfer protocols are asynchronous and fully handshaken. The
priority interrupt bus provides real-time interrupt services to the system. The
allocation of bus mastership is performed by the arbitration bus, which allows
to implement round robin and prioritized arbitration algorithms. The utility
bus provides the system with power-up and power-down synchronization. The
mechanical specifications of boards, backplanes, subracks, and enclosures are
based on 297 specification, also known as the Euroboard form factor.
Content
1. Introduction
1.1 Objectives
1.2 Interface System Elements
1.2.1 Basic Definitions
1.2.2 Basic Structure
1.3 Specification Diagrams
1.4 Terminology
1.4.1 Signal Line State
1.4.2 Use of the Asterisk
1.5 Protocol
1.5.1 Interlocked Bus Signal
1.5.2 Broadcast Bus Signal
1.6 System Examples and Explanations
2. Data Transfer Bus
2.1 Introduction
2.2 Data-Transfer-Bus Lines
2.2.1 Addressing Lines
2.2.2 Address-Modifier Lines
2.2.3 Data Lines
2.2.4 Data-Transfer-Bus Control lines
2.3 DTB Modules — Basic Description
2.3.1 Master
2.3.2 Slave
2.3.3 Bus Timer
2.3.4 Location Monitor
2.3.5 Addressing Modes
2.3.6 Basic Data Transfer Capabilities
2.3.7 Block-Transfer Capabilities
2.3.8 Read-Modify-Write Capability
2.3.9 Unaligned Transfer Capability
2.3.10 Address-Only Capability
2.3.11 Interaction Between DTB Functional Modules
2.4 Typical Operation
2.4.1 Typical Data-Transfer Cycles
2.4.2 Address Pipelining
2.5 Data-Transfer-Bus Acquisition
2.6 DTB Timing Rules and Observations
3. DTB Arbitration Bus
3.1 Introduction
3.1.1 Types of Arbitration
3.2 Arbitration Bus Lines
3.2.1 Bus Request and Bus Grant Lines
3.2.2 Bus Busy line (BBSY*)
3.2.3 Bus Clear Line (BCLR*)
3.3 Functional Modules
3.3.1 Arbiter
3.3.2 Requester
3.3.3 Data-Transfer-Bus Master
3.4 Typical Operation
3.4.1 Arbitration of Two Different Levels of Bus Request
3.4.2 Arbitration of Two Bus Requests on the Same Bus Request Line
3.5 Race Conditions Between Master Requests and Arbiter Grants
4. Priority Interrupt Bus
4.1 Introduction
4.1.1 Single Handler Systems
4.1.2 Distributed Systems
4.2 Priority Interrupt Bus lines
4.2.1 Interrupt Request Lines
4.2.2 Interrupt Acknowledge Line
4.2.3 Interrupt Acknowledge Daisy-Chain
4.3 Priority Interrupt Bus Modules — Basic Description
4.3.1 Interrupt Handlers
4.3.2 Interrupters
4.3.3 IACK Daisy-Chain Driver
4.3.4 Interrupt Handling Capabilities
4.3.5 Interrupt Request Capabilities
4.3.6 Status/ID Transfer Capabilities
4.3.7 Interrupt Release Capabilities
4.3.8 Interaction Between Priority Interrupt Bus Modules
4.4 Typical Operation
4.4.1 Single Handler Interrupt Operation
4.4.2 Distributed Interrupt Operation
4.4.3 Example: Typical Single Handler Interrupt System Operation
4.4.4 Example: Prioritization of Two Interrupts in a Distributed Interrupt System
4.5 Race Conditions
4.6 Priority Interrupt Bus Timing Rules and Observations
5. Utility Bus
5.1 Introduction
5.2 Utility Bus Signal Lines
5.3 Utility Bus Modules
5.3.1 The System Clock Driver
5.3.2 The Serial Clock Driver
5.3.3 The Power Monitor
5.4 System Initialization and Diagnostics
5.5 Power Pins
5.6 Reserved Line
6. Electrical Specifications
6.1 Introduction
6.2 Power Distribution
6.2.1 DC Voltage Specifications
6.2.2 Pin and Socket Connector Electrical Ratings
6.3 Electrical Signal Characteristics
6.4 Bus Driving and Receiving Requirements
6.4.1 Bus Driver Definitions
6.4.2 Driving and Loading Rules for All lines
6.5 Backplane Signal Line Interconnections
6.5.1 Termination Networks
6.5.2 Characteristic Impedance
6.5.3 Additional Information
6.6 User-Defined Signals
6.7 Signal Line Drivers and Terminations
7. Mechanical Specifications
7.1 Introduction
7.2 Boards
7.2.1 Single-Height Boards
7.2.2 Double-Height Boards
7.2.3 Board Connectors
7.2.4 Board Assemblies
7.2.5 Board Widths
7.2.6 Board Warpage, Lead Length, and Component Height
7.3 Front Panels
7.3.1 Handles
7.3.2 Front Panel Mounting
7.3.3 Front Panel Dimensions
7.3.4 Filler Panels
7.3.5 Board Ejectors and Injectors
7.4 Backplanes
7.4.1 Backplane Dimensional Requirements
7.4.2 Signal Line Termination Networks
7.5 Assembly of Subracks
7.5.1 Subracks and Slot Widths
7.5.2 Subrack Dimensions
7.6 Backplane Connectors and Board Connectors
7.6.1 Pin Assignments for the J1/P1 Connector
7.6.2 Pin Assignments for the J2/P2 Connector
Annex A Glossary
Annex B Signal Line Description
Annex C Use of the SERCLK and SERDAT* Lines
Annex D Metastability and Synchronization
D1 Introduction
D2 A Simple Nand Latch
D3 Edge Triggered Flip-Flops
D4 Synchronous versus Asynchronous Design
D5 Determining Flip-Flop Resolution Times
D6 Sample Circuits
D6.1 Handling the Arbitration Daisy-Chain Asynchronously
D6.2 Handling the Arbitration Daisy-Chain Synchronously
D6.3 Handling the Interrupt Acknowledge Daisy-Chain Asynchronously
auto An Asynchronous Arbiter
D7 Additional Information
Annex E Permissible Capability Subsets
E1 Introduction
E2 Permissible Subsets of DTB Modules
E2.1 Permissible Subsets of Addressing Capabilities
E2.1.1 Address Size
E2.1.2 Address-Only Cycles
E2.2 Permissible Subsets of Data-Transfer Capabilities
E2.2.1 Data Size
E2.2.2 Unaligned Transfer Capability
E2.2.3 Block Transfers Capability
E2.2.4 Read-Modify-Write Capability
E3 Interoperability Among Arbitration Bus Modules
E3.1 Capabilities of the Arbiter
auto Capabilities of the Requester
E4 Interoperability Among Priority Interrupt Bus Modules
