ANSI/IEEE Std 1000-1987 An American National StandardIEEE Standard for an 8-Bit Backplane Interface: STEbus -Description

Content

• 1. General
• • 1.1 Scope
  • 1.2 Features
  • 1.3 Objects
  • 1.4 Definitions
  • • 1.4.1 General System Terms
    • 1.4.2 Signals and Paths
    • 1.4.3 Generic Signal Names
    • 1.4.4 Notation for Bus Signals
  • 1.5 Logical and Electrical State Relationships
• 2. Functional Description
• • 2.1 System Controller
  • 2.2 Arbiter
  • 2.3 Masters
  • • 2.3.1 Master Types
    • 2.3.2 Master Modes
  • 2.4 Slaves
• 3. Signal Lines
• • 3.1 Information Lines
  • • 3.1.1 Address Lines (A〈19..0〉)
    • 3.1.2 Data Lines (D〈7..0〉)
    • 3.1.3 Command Lines (CM〈2..0〉)
  • 3.2 Synchronization Lines
  • • 3.2.1 Address Strobe (ADRSTB*)
    • 3.2.2 Data Strobe (DATSTB*)
    • 3.2.3 Data Transfer Acknowledge (DATACK*)
    • 3.2.4 Transfer Error (TFRERR*)
  • 3.3 Attention Request Lines (ATNRQ〈7..0〉*)
  • 3.4 Bus Allocation Lines
  • • 3.4.1 Bus Request Lines (BUSRQ〈1..0〉*)
    • 3.4.2 Bus Acknowledge Lines (BUSAK〈1..0〉*)
  • 3.5 Utility Lines
  • • 3.5.1 System Clock (SYSCLK)
    • 3.5.2 System Reset (SYSRST*)
  • 3.6 IEEE Std 1000 Bus Connector Pin Allocations
  • • 3.6.1 Connector Type
    • 3.6.2 Connector Pin Allocation
• 4. Arbitration
• • 4.1 Arbitration Algorithm
  • 4.2 Bus Requests
  • 4.3 Bus Grants
  • 4.4 Control Allocation Sequence
• 5. Data Transfer Protocol
• • 5.1 Read Sequence
  • 5.2 Write Sequence
  • 5.3 Read-Modify-Write Sequence
  • 5.4 Vector-Fetch
  • 5.5 Burst Transfer Sequences
  • 5.6 General Data Transfer Rules
  • 5.7 Transfer Error
  • 5.8 System Time-Out
• 6. Inter-Board Signaling
• • 6.1 Overview
  • 6.2 Attention Request Lines (ATNRQ〈7..0〉*)
  • • 6.2.1 Attention Request Priority
  • 6.3 Response to Interrupt Attention Requests
  • • 6.3.1 Implicit Response
    • 6.3.2 Explicit Response
    • 6.3.3 Local Action Response
  • 6.4 Excluded Utilizations of Attention Request Lines
• 7. Electrical Specifications
• • 7.1 Power Supplies
  • • 7.1.1 Supply Tolerances
    • 7.1.2 Power Distribution
    • 7.1.3 Power-Failure
  • 7.2 Board-Electrical Requirements
  • • 7.2.1 Connector-Electrical Specification
  • 7.3 Driver and Receiver DC Characteristics
  • 7.4 Signal DC Characteristics
  • 7.5 Signal AC Characteristics
  • 7.6 Backplane AC Specifications
  • • 7.6.1 Transmission-Line Environment
    • 7.6.2 Characteristic Impedance
  • 7.7 Termination Networks
• Annex A Applicable IEC Specifications
• Annex B Recommended Bus Termination Arrangement

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