Design of High-Performance Microprocessor Circuits

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The IEEE 1394 ( a.k.a. FireWire®) standards effort started in 1986 at the request of the membership of the IEEE Microcomputer Standards Committee to unify the different serial bus ses originally proposed as parts of the IEEE 1014 VME, IEEE 1296 Multibus II, and IEEE 896 FutureBus+® efforts. As the proposed standard was developed, it attracted more interest from those that needed a much improved external I/O interconnect for multimedia information and for mass storage. This added the requirements for isochronous transport, much higher data rates, and a more rugged cable and connector system.

IEEE Std. 1394-1995 describes a serial bus that provides the same services as modern IEEE-standard parallel buses, but at a much lower cost. It has a 64-bit address space, control registers, and a read/write/lock operation set that conforms to the IEEE Std. 1212-1991, Command and Status Register (CSR) standard. This simplifies bridging between the Serial Bus and the other interconnects using the IEEE 1212 architecture: IEEE Std. 896-1991, Futurebus+® and IEEE Std. 1596-1992, Scalable Coherent interface (SCI).

There are two physical environments for the Serial Bus: the backplane environment uses two-single-ended signals on a broadcast multitapped bus using backplane transceiver logic (BTL) or emitter coupled logic (ECL) transceiver technology at 49.152 Mbit/s or enhanced transistor-transistor logic (TTL) transceiver technology at 24.576 Mbit/s. In all cases, bus arbitration on the backplane is done using a dominant-mode-logic bit serial approach. The cable environment uses two low-voltage differential signals to connect devices in a noncyclic topology at 98.304 Mbit/s, 196.608 Mbit/s, and 393.216 Mbit/s data races.

The cable arbitration system uses a self-configuring hierarchical request/grant that supports hot plugging and widely varying physical topologies. In addition to standard read/write/lock transactions, the Serial bus provides extensive time-based services, including isochronous data transport (guaranteed latency and bandwidth) and an accurate submicrosecond global timebase for synchronizing events and data.

Highlights of a Serial bus include:

Automatic assignment of node addresses — no need for address switches.
Variable speed data transmission based on ISDN compatible 1 bit rates from 24.576 Mbit/s for TTL backplanes to 49.152 Mbit/s for BTL backplanes to 98.304 Mbit/s, 196.608 Mbit/s, and 393.216 Mbit/s for the cable medium.
The cable medium allows up to sixteen physical connections (cable hops), each up to 4.5 m, giving a total cable distance of 72 m between any two devices. Bus management recognizes smaller configurations to optimize performance.
Bus transactions that include both block and single quadlet reads and writes,as well as an "isochronous" mode that provides a low-overhead guaranteed bandwidth service.
A physical layer supporting both cable media and backplane buses.
The cable medium allows up to sixteen physical connections (cable hops), each up to 4.5 m, giving a total cable distance of 72 m between any two devices. Bus management recognizes smaller configurations to optimize performance.

Consistent with ISO/IEC 13213:1994

 

Copyright ©2006 IEEE

(m.plessel@ieee.org)
URL: http://standards.ieee.org/micro/

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