Description: This standard is one in a family of Futurebus+TM standards. The Futurebus+ standards provide a set of tools with which to implement a bus architecture with performance and cost scalability over time for multiple generations of single- and multiple-bus multiprocessor systems. This standard provides fault tolerant extensions to Futurebus+ standards. As such, this standard provides the logical layer requirements for the transmission of data in a fault tolerant environment. When used in conjunction with other IEEE standards, the details to develop modular, open-architecture-based systems fulfilling user needs across a wide computing spectrum are available.
Oversight Committee: C/MSC - Microprocessor Standards Committee 
Sponsor: IEEE Computer Society 
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