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IEEE STANDARD

1800.2-2017 - IEEE Approved Draft Standard for Universal Verification Methodology Language Reference Manual

Description: The Universal Verification Methodology (UVM) can improve interoperability, reduce the cost of using Intellectual Property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM class library, the implementors of tools supporting the class library, and the users of the class library.
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