IEEE SA - 1364.1-2002 - IEEE (Replaced)IEEE Standard for Verilog Register Transfer Level Synthesis

Description: Standard syntax and semantics for Verilog HDL-based RTL synthesis are described in this standard.

Working Group: VLOGSyn - Verilog Register Transfer Level Synthesis Working Group

Oversight Committee: C/DA - Design Automation

Sponsor: IEEE Computer Society

Get This Standard

Buy Purchase a copy of this standard Buy

Buy VuSpec CD ROM This standard can be purchased as part of the following VuSpect CD:

- IEEE VuSpec: 2007 Electronic Design Automation Buy

Access with Subscription Standards Online subscribers can access this standard in IEEE Xplore Digital Library. Access Learn More

IEEE-SA Individual Members save 10% (on average)* on most standards purchased through IEEE.

* actual savings vary per standard