1296-1987 - IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II
Description: This IEEE standard describes a high-performance backplane intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed address/data, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data over the bus. This provides high-performance interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages.