Description: A common bus architecture (which includes functional components-modules, nodes, units-and their address space ,transaction set, CSRs, and configuration information) suitable for both parallel, serial buses is provided in this standard. Bus bridges are enabled by the architecture, but their details are beyond its scope. Configuration information is self-administered by vendors, organizations based upon IEEE Registration Authority company_id.
Working Group: 1212_WG - Control and Status Registers Working Group
Oversight Committee: C/MSC - Microprocessor Standards Committee 
Sponsor: IEEE Computer Society 
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