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IEEE STANDARD

1149.10-2017 - IEEE Approved Draft High Speed Test Access Port and On-chip Distribution Architecture

Description: Circuitry that may be built into an integrated circuit to assist in the test, maintenance and support of assembled printed circuit boards, assembled multi-die packages and the test of die internal circuits is defined. The circuitry includes a high-speed TAP (HSTAP) with a packet encoder/decoder and distribution architecture through which instructions and test data are communicated. The standard leverages the languages of IEEE Std. 1149.1 in order to describe and operate the on-chip circuits.
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