IEEE Standards Association
IEEE STANDARD
1076.6-2004 - IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis
Description: This document specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.
- Status:
Oversight Committee: C/DA - Design Automation 
Sponsor: IEEE Computer Society
Get This Standard
Buy Purchase a copy of this standard Buy
Buy VuSpec CD ROM This standard can be purchased as part of the following VuSpect CD:
- IEEE VuSpec: 2007 Electronic Design Automation Buy
Access with Subscription 
Standards Online subscribers can access this standard in IEEE Xplore Digital Library. Access Learn More
Standards Online subscribers can access this standard in IEEE Xplore Digital Library. Access Learn More
Additional Resources
Join IEEE-SA & Save!
IEEE-SA Individual Members save 10% (on average)* on most standards purchased through IEEE.* actual savings vary per standard
Get Networked.
Stay Connected.
Already involved with IEEE-SA? Don't be shy ... shout it out. Advertise your participation on your social networks.
