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ANSI/IEEE 1076.6-1999 - IEEE Standard for VHDL Register Transfer Level Synthesis

Description: A standard syntax and semantics for VHDL register transfer level (RTL) synthesis is defined. The subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis is defined, along with the semantics of that subset for the synthesis domain.
  • Status:Superseded STDHelp

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