Description: The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.
Oversight Committee: C/DA - Design Automation
Get This Standard
Buy Purchase a copy of this standard Buy
Access with Subscription Standards Online subscribers can access this standard in IEEE Xplore Digital Library. Access Learn More