IEEE-SA SYMPOSIUM ON EDA INTEROPERABILITY
TechMart, Santa Clara, CA
Thursday, 24 October 2013
|9:00 am - 10:00 am||Registration, Coffee, Continental Breakfast|
|10:00 am - 11:00 am||Opening Session: "Passing on the Interoperability Torch"
-Dr. Rich Goldman, Synopsys
|Keynote 1: "Interoperability at the Intersection of Technology Innovation and Business Economics"
-Dr. Konstantinos Karachalios, Managing Director of IEEE-SA
|“EDA Interoperability: Smoke, Mirrors and Crystal Ball”
-Dr. Karen Pieper, Technical Coordinating Committee Chair, Accellera Systems Initiative
|11:00 am - 12:00 pm||Session 1: Interoperability Challenges: Power Management in Silicon|
|"IEEE 1801 Low Power Format: Impact and Opportunities"
-Erich Marschner, Vice Chair of IEEE P1801 Working Group, Verification Architect, Mentor Graphics
|“Power Intent Constraints: Using IEEE1801 to improve the quality of soft IP”
-Stuart Riches, Principal Engineer, ARM
|"Power Intent Verification: Using IEEE1801 for the verification of ARM Cortex A53 processor"
-Adnan Khan, Senior Engineer, ARM
|12:00 pm - 1:45 pm||Lunch|
|Keynote 2: "How did UVM begin: Interoperability Standards at Freescale and the Standards of the future"
-Hillel Miller, Emulation and SOC IP Verification Manager for Digital Networking, Freescale Semiconductor
|Tenzing Norgay Interoperability Award Presentation|
|Panel: "IP Interoperability in EDA World: Domain of Possibilities"
-Moderator: Edward Sperling, Editor in Chief, Semiconductor Engineering
|1:45 pm - 2:45 pm||Session 2: Interoperability Challenges: Custom Design|
|"Experience with Custom Design Flow and Interoperability"
-Phillip LaPlace, AMS Methodology Manager, Freescale
|"TSMC PDK Overview and Challenges for New Technology Nodes"
-David Lan, Senior Manager, Design Automation & Methodology, TSMC NA
|2:45 pm - 3:00 pm||Break|
|3:00 pm - 4:30 pm||"EDA 2020: Unconference" Participative Roundtable
-Host: Karen McCabe, Sr. Director, IEEE-SA
|4:30pm - 6:00 pm||Reception|