CFP IEEE P1800.2™ WG
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Scope of the Project
The IEEE P1800.2™ Standard for Universal Verification Methodology Language Reference Manual establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.

Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry.

Need for the Project
As the electronics industry builds more complex systems involving large numbers of components, the challenge of verifying such systems multiplies by orders of magnitude. In order to bring costs and time to market down, standardization must happen to enable as much modularity and reuse across verification components as possible. The UVM standard will propagate an API that will manage this explosion in verification complexity, allowing the entire industry to write and reuse verification components both (a) internally in companies having geographically widespread teams, and (b) externally between vendors and user companies in the electronics industry, who are developing, selling and using verification components

Call for Contribution
Please review the IEEE  P1800.2 ™ PAR and, if you are interested in participating, Register for the first working group scheduled to occur on August 6th, 2015 from 12pm – 2pm Eastern Daylight Time (EDT) / 9am – 11am Pacific Daylight Time (PDT). 

Please feel free to connect with the Working Group Chair, Thomas Alsop at or IEEE-SA staff Jonathan Goldberg at directly for further information.

Working Group Membership will be established during the first working group meeting. Thereafter, membership will be granted after an entity representative attends two (2) consecutive meetings.

Please note: working group membership is entity-based for this project: one company, one vote. An entity shall be, at a minimum, an IEEE-SA Basic Corporate Member to attend the working group meetings, however, the entity will not be able to participate, vote within the working group or provide technical contributions. As an IEEE-SA Advanced Corporate Member, the entity may declare their intent to join the working group and pay any service fees, if established, to become a fully participative voting member of the working group. Additionally, only working group voting members may fill any vacant Officer position(s). Any entities attaining working group membership shall fulfill the requirements determined by the Sponsor and the working group.

An entity may join one (1) entity-based working group meeting as an Observer to determine whether or not they wish to continue participation within the working group by becoming an IEEE-SA Basic or Advanced Corporate Member.

For other information on participation in entity-based working group, see sub clause of the IEEE-SA Standards Board Bylaws.

For more information regarding IEEE-SA Corporate Membership, please visit

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