Is the vendor or the IP department certified for a industry quality standard like e.g. ISO9001, CMMI, ISO/TS, 16949 or others?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the development process for IP defined and documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the documented development process for IP followed consistently?At a minimum, all new IP needs to use this process.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are the IP Quality Assurance processes independently audited by a group not affiliated with the creation?This is by a group not associated with the development of the IP, either another group internal to the company or a third party.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does a process for continuous improvement of IP quality exist and is this process followed consistently? A systematic process needs to be in place which makes sure that quality issues are recognized, reported and addressed.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does a process for measuring customer satisfaction exist and is this process used consistently?This process should track # of bugs, response times for questions & issues,…IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there an audit process to check compliance to the design, verification and QA process?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the QIP used consistently?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are the EDA tools and versions used for developing the IP documented?Note that this could be different from the EDA tools and versions SUPPORTED by the IP.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the verification flow defined and documented and can this document be made available to the user?Verification flow in this context means how the vendor assures that the IP will meet the specification. This document needs to cover the following: - Which verification methodologies are used (RTL Simulations, Random or Directed Random Simulations, Equivalency Checking, Static Timing Analysis, Spice Simulations, FPGA Prototyping,…)? - Which tools are used for verification of the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does a detailed and coordinated test plan exist and can this document be made available to the user?The test plan is a list of detailed scenarios which have been verified during functional verification.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is a system for measuring quality of verification used and can the results be made available to the user?Systems for measuring verification quality are: - Code Coverage Tools - Functional Coverage Tools ...IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is the IP verified in the system context?E.g. integrated with other IP both on and off chip, SW application running, etc. IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the requirements change process for IP defined, documented and followed consistently?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Has the IP been used in real production environment?Beta or first-use IP and VIP carries additional risk compared to those that have been used extensively.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does a process exist and is this process used consistently to make sure that deliverables are verified to be complete and correct?This process needs to make sure that no deliverables are missing and that the deliverables can at least be used with the indented tools without syntax errors.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do the deliverables quality checks include integrating the IP in the typical SOC design context?This QA goes beyond mere deliverable existence and syntax checking as it exposes the IP to the typical design context, e.g. interfaces and related IPIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do the deliverables quality checks include integrating the IP using the typical design flow context?This QA goes beyond mere existence and syntax checking as it exposes the deliverables to the design flows (i.e. specific tools). This may be at the RTL level only, or include silicon implementations at the FPGA or test chip level. The intent is to QA the IP in more than a standalone configuration, i.e. interfacing to other blocks.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Can the details of the Deliverables QA be made available to the user?This document needs to cover the following aspects: - Which deliverables have been tested? - Which tools have the deliverables been tested with? - Which design flow was used for this deliverables QA? - Which design context was used for integrating the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does the revision control scheme clearly distinguish new revisions from older ones?This also implies that the revision control scheme is ONLY used for sequential revisions of this IP, not for e.g. for implementation alternatives.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the revision control scheme permit the user to select a specific revision?For designs in progress the user needs to have the option of sticking to an older revision of the IP or upgrading to the newest revision.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5At any step of the design flow, can the user identify the IP revision used?Being able to identify the revision which is being used is important for interactions between the user and the IP vendor.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Can the user verify whether a particular file of the deliverables belongs to a certain revision of the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are revisions incremented in a sensible manner ensuring that changes that don't affect the actual sources of the IP do not require a rebuild of designs in progress?Sources of the IP are RTL code, gate level netlists, and layout database, whereas supporting deliverables are documentation, scripts, simulation environment. Changes to supporting deliverables only should not require an update of the IP source, hence should at most only be indicated by a minor revision step (ex 2.1 to 2.1a or 2.2). Changes in the source code functionality or interface should be clearly identifiable by the revisioning scheme.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all changes made for each revision well documented?The following needs to be documented for each revision: - What has changed? - Why was the change necessary? - When was the change made? - How does it affect the user?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are end-of-life notices for IP given well in advance (at least 6 months)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is the revision control scheme and related guidelines fully documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the revision control scheme permit the user to select a specific version for any file?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the revision control scheme permit an association of all issues to the corresponding revision?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the user have control over when deliverables are updated at his site?Preference of Pull (User pulls new deliverables at his convenience) over Push (deliverables are automatically pushed out and updated at user's site).IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the user get notified automatically if the Errata documenting bugs and workarounds gets updated?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Will the IP Provider work with the customer to determine whether the customer is affected by an errata?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the user get notified automatically if supporting deliverables of the IP change?This is particularly important for PULL-based distribution systems, where without notification the user would run risk of missing an update in the documentation, scripts, etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the user get notified automatically if new features or new revisions of the IP become available?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does a scheme for classifying IP with regards to its maturity exist and is it used consistently?The more mature a piece of IP is, the less risk is involved in using the IP. An IP maturity classification scheme should include aspects like: - Is design and verification done for this IP? - Can customer designs tape out using this IP? - Does silicon using this IP exist? - Is silicon using this IP in volume production? Maturity classification schemes used by major IP Vendors are for example: {TSMC - 0, 1, 3, 5}, {ST - Mat10, Mat20, Mat30, Mat40}, {LSI Logic - Preliminary release, Early Access release, Design-In release, General release}, etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are the IP and the associated deliverables provided in a standardized, consistent manner?The same delivery mechanism and structure is used to deliver all IP. IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is a classification scheme used that clearly distinguishes IP adhering to QIP from IP that doesn't?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does all new IP adhere to QIP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is a naming convention in use which avoids naming conflicts while in use with IPs (or VIP) from other departments or vendors?This applies to the IP as well as to the verification components provided with the IP.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are the liabilities and responsibilities in case of a respin due to issues with the IP documented?This is likely to be included in the contract, but must be identified prior to purchase. Note that this requirement does not imply what the liabilities and responsibilities are.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is a problem reporting infrastructure and corresponding processes in use to make sure that issues encountered by the user are addressed according to their severity in a timely manner?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is knowledgeable Technical Support available for answering questions?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does a knowledge-database to which a user has access to exist?This may include FAQ's, searchable issues/resolutions, usage examples, etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Can the IP be evaluated before purchase?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Are the evaluation deliverables well documented?This documentation needs to cover: - How to obtain the evaluation deliverables - How to install the evaluation deliverables - How to use the evaluation deliverables - Limitations of the evaluation deliverables wrt. to the full packageIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline245Are bug fixes/updates available 24/7 for electronic download IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has the company secure network facilities for on-site support?Such as VPN and "cleanroom"IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Has the company capacity for on-site support?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does the documentation for released IP reflect the actual behavior and characteristics of the IP and is this documentation updated if the IP changes?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the documentation cover all aspects necessary to successfully integrate the IP into a system?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do all documents leverage templates which are used corporate wide?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Are all relevant industry standard formats listed in the comment supported?The industry standard formats which should be supported are: - Verilog and/or VHDL (for Soft IP) - Spirit - SDC (for Soft IP) - LEF (for Hard IP) - GDS2 (for Hard IP) - SystemC or SystemVerilog (for VIP) Requirements to specific languages and language revisions must be documented.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are the EDA tools and versions supported by the IP documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has the company been in existence for more than 5 years?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does the company have at least 50 employees?The reasoning for this requirement is that a company with more employees is less likely to go out of business. Therefore the customer can have a higher confidence that the IP will still be supported in a couple of years down the road. Indicate in the comment section the number of employees dedicated to IP development and support. IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is the company a publicly traded company?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Can information regarding the profitability of the company be made available?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Can customer references be made available?If possible, indicate the specific applications in which a product has been used.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has the IP been successfully utilized in creating an SoC by a team other than the IP development team?This provides some level of assurance that the IP can be reused.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there a customer willing to be a reference for this IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Has the IP been used to realize an actual IC product or FPGA and does the functionality of this IP block work as expected?Answer NO if it has not been realized in an actual IC. Answer NO if the IC functionality failed to meet the specifications of the IP block.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does training for the IP exist?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do you take advantage of industry standard compliance testing if applicable and available?System protocol compliance verification verifies that the IP complies to the industry standard protocol supported by the IP (e.g. USB2.0). Answer 'y' if not applicable.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has the IP passed the industry standard compliance certification testing?Answer 'y' if not applicable.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule563Has a Product Brief (e.g. short 2-3 pg datasheet) been developed?Answer YES if the Product Brief has been developed and is available for customer use.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is an IP Integration manual or chapter available?Does the IP contain an integration manual or integration application noteIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the IP integration section define the deliverables?Does this document clearly indicate the purpose of each deliverable?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1066Does the document fully define the interfaces to the IP?Does this document provide a definition of all interfaces, their function & electrical characteristics and any interface requirements?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1066Does the document define naming conventions?Does this document define the naming convention used within the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule566Is there a means of verifying the completeness of the deliverables?Does this document contain a section that clearly shows you how to set up and verify that you received a complete and working IP block?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule566Does the document describe how to instantiate the IP component?Does the document provide you with an SoC integration instantiation template and shows you how to connect the block to the rest of the SoC?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule566Does the document provide instructions for how to build an environment using this component?Does this document include a chapter that describes the simulation and setup scripts, the tool chain used and how to build the standalone testbench?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule566Are area estimates for IP implementation in a representative technology provided?Does this document contain a section that describes a sample technology library and the expected performance characteristics of an implementation in terms of power and area given that technology?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule566Are power estimates for IP implementation in a representative technology provided?Does this document contain a section that describes a sample technology library and the expected performance characteristics of an implementation in terms of power and area given that technology?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule566Are all configuration parameters clearly defined and documented?If it is not clear what the configuration parameters are or how to use them, then answer NOIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1066Is the order of file compilation clearly documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule566Is the functionality of each interface clearly defined?Answer YES if each interface is clearly defined and you can readily understand how to design logic to support the interface definitions.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1066Is the number of clock domains and clock frequencies well documented? Required clock frequencies and associated phase lock loops (PLL) and external timing requirements (setup/hold and output timing) fully documented.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1066Does the documentation clearly describe how to set up the verification environment and run through the self-test diagnostics?Using the provided documentation, setup the environment and run the tests. If the procedure is clear, answer YES, otherwise if the procedure requires you to contact the supplier in any manner or if there is no documentation, then enter NO.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1066Is the default configuration of Verification Environment well-documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule566If formal verification methods are used for this design representation, is the appropriate data supplied?The data includes identification of any tools and versions used; description of the process used to improve coverage; tests that were generated as part of the verification environment. If formal methods were not used, answer this question "N".IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule566Is the functional coverage methodology documented and is this document available to the IP integrator to assess the quality of the verification?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule566Are the input, output, bi-directional, and internal signal timing specifications documented and available to the IP integrator?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule566Does the documentation provide a manifest of all the deliverables and a description of the deliverables, file names (meaningful names), and size (in KB)? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule566Is an IP reference manual available?Does the IP contain a hardware reference manual or datasheet?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the document contain a functional description of the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1085Does the document contain an Architectural Overview?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1085Does the document fully define the interfaces to the IP?Does the document include a complete interface definition of all input, output and bi-directional pins and their functions?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1085Does the document contain timing diagrams?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1085Does this component contain a programmable instruction set ?If the reference manual does not exist, then do not answer remaining questions in this sectionIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Is a programmers reference manual or section available that completely specifies how to program the device?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1090Does this component contain registers that can be configured to control its functionality?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Is there a register map section present in the hardware reference manual or a separate document available that describes how to program the registers?Is the programmability of the register set completely documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1092Are there release notes available?Answer Yes to all subsequent questions if this is the first version.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are the differences from the previous release clearly described?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1094Are known, unresolved and outstanding issue described?Does the document indicate all unresolved issues? Answer yes if there are no unresolved issues.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative1094Is the IP designed to support instance by instance configurability?Can you configure each instantiation of the IP separately from other instantiations?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is the configuration accomplished thru the establishment of parametric calling routines rather than modifying hard coded constants?It is highly desirable that all configurability be programmatic rather than constant-based.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule597Does the verification environment support configurable IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are the parameters modified by the user validated automatically for both the IP and the verification environment?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule599Are synthesis scripts with timing constraints provided?Having synthesis scripts and timing constraints available significantly reduces design integration time. The timing constraints need to be written in a way to allow technological scaling - e.g. with constants used for key parameters (clock periods etc).IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are scan insertion scripts provided?Having scan insertion scripts available reduces design integration time. These scripts should address the scan flop insertion at the IP level as opposed to scan chain stitching at the SoC level.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the IP include a MAKE file or other means of installation or compilation?IP blocks are frequently comprised of a set of files that need to be compiled in a specified order. IP providers are encouraged to simplify this compilation by providing their customers with compilation scripts that automate this process. Enter YES if this IP block is delivered with a script, MAKE file or other means of automatic compilation.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does the IP have a documented and well ordered directory structure?How straight forward is directory structure? How easy is it to incorporate component's directory structure with structure of product being developed? IP has a well organized directory structure. IP directories have a ReadMe file that explain the functionIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Will the build environment automatically create any of the directories or intermediate working files it needs as part of the build process?Answer YES if, other than setting up the root directory, the build environment will automatically handle the creation of the sub-directory trees that it requires.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Other than tool dependent configuration files, is the IP designed to be tool independent?Answer NO if the IP relies upon vendor specific language extensions or environments.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Except for the top-most level, are all file pathnames relative?You should answer NO to this question if the IP refers to absolute path names to a specific directory rather than relative pathnames to the root of the IP design tree.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all required files included within the IP delivery?The IP integrator should not be required to locate or download files from other sources in order to integrate an IP block into and SoC design.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are there no internal tri-state buses or wired-and logic?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all referenced modules or packages simulation and synthesis tool independent?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the IP design independent of the library vendor?Answer NO if the IP depends upon a specific memory library supplier or other specific library.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the IP source code provided?Answer YES if the source code is provided as a deliverable or if the IP source code can be purchased or licensed.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there a model available at a suitable level of abstraction to enable system level evaluation?If the IP is a programmable processor, then answer YES if an Instruction Set Architecture model is available. If the IP is a complex mixed signal device, answer YES if a Verilog or VHDL AMS model is available. Answer YES if a C++ model is available for this block.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are the interfaces described in a way to enable transaction-level modeling?Are interfaces functionally grouped? (address, data, control, interrupt, etc)IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is an application programming interface (API) library required for this IP?For example, a synthesizable modem.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Is the API provided with the IP?If the API is required, then it must be providedIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10115Is the API fully documented?The API document must clearly indicate all subprogram functionality and interfaces.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10115Does the IP connect to a fully documented industry standard interface?Answer YES if the IP interfaces to an industry standardIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Is the IP's interface fully compliant with this standard?Answer NO if the IP is not fully and 100% compliantIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10118Can the IP be put into a deterministic reset condition either synchronously or asynchronously?It is essential that some form of IP reset be present and that the reset state is deterministic.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the system require the interaction between more than one clock domain?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nMitigable0Does the IP come with a self-checking verification environment?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is the verification environment tolerant to slight timing differences between gate-level implementations and RTL level representations?Answer YES if the environment can handle cycle-slippage for asynchronous interfaces which would not make the runs identical.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5122Does the IP include a reusable verification component such as an eVC, SystemC, Vera, C++ or similar verification component?Answering YES wins points and enables the following questions IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does the reusable verification component documentation clearly indicate the methods available for use within the verification component?Answer YES if the documentation of the verification component is clearly understood without having to contact the supplierIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10124Does the documentation describe how to use the verification components in an SoC verification environment?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5124Can the verification component be extended to include additional functionality?Answer YES if the methods are extensible or polymorphicIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2124Might the design require embedded memories?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Is the memory interface parametric in size?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2128Is a behavioral (high-level) model of the embedded memory included?It is recommended that both a detailed and a high-level behavioral model of memory be supplied.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2128Does the design contain an internally generated conditional reset?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Has this conditional reset been generated within a separate top level module?If a conditional reset is required, then create a separate signal for the reset line and isolate its generating logic in a separate module.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5131Does each clock domain have an independent reset line?Separate resets per clock domain so that de-assertion can be synchronized to the clock. This also allows the reset to be applied synchronously if the SoC requires it.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the operation of the IP predictable when the reset is released?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has the design avoided the use of combinational feedback; (i.e. the looping of combinational processes)?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Does the design require that a multi-cycle path be used?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nMitigable0Are point-to-point exceptions well defined and maintained within a single module?Answer NO if not well defined or not maintained in a single moduleIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5136Does the design contain asynchronous logic?Asynchronous logic may introduce timing uncertainties. If asynchronous logic is unavoidable, the following question is intended to ensure that it is correctly addressed.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nMitigable0Is all unavoidable asynchronous logic partitioned into a separate module?IP is partitioned into modules which are synchronous and register based. Latches are used only to implement small memories and FIFOs. FIFOs and memories designed so that they are synchronous and edge triggered. IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5138Are clock buffers instantiated only as a result of clock tree synthesis?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5For each module of a hierarchical design, do all output signals from the module come directly from registers?IP uses synchronous buses.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is one or more internally generated or gated clocks required?List all internally generated or gated clocks.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Are all generated clocks consolidated into a separate module at the top level of the hierarchy?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5142Does the IP contain any asynchronous input signals?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Has metastability protection been used?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10144If the design uses positive and negative edge flip-flops, is the worst case duty cycle modeled and documented for timing analysis and synthesis?Answer Y if the design only uses a single edge of the flops. Single clock phase flip-flops (either positive-edge or negative-edge) used throughout design. Recommended use of positive-edge flip-flops for standardization.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10If the design uses positive and negative edge flip-flops, are the positive edge triggered flip-flops in a different module than the negative edge triggered flip flops?Answer Y if the design only uses a single edge of the flops.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is it possible to insert full-scan into this IP block?The design should intend that full-scan can be applied. In particular: All FFs can be converted to scan FFs and controlled within the module. All multiple driven signals have combinatorial logic that ensures only one signal driver (including test mode) The expected use is that all inputs are controllable and all outputs observable. IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has the trial ATPG coverage been run and results made available?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have BIST requirements been addressed and documented?BIST would refer to memory BIST or logic BIST as the case may be applicable to your designIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have test isolation requirements been addressed and documented? This is applicable only if vectors are provided.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Can the synthesis script accept the soft IP parameter settings defined elsewhere?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the IP include timing constraints?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are "Don't touch" attributes specified on clock and asynchronous reset networks and included in the synthesis scripts?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does each executable script contain a "-h" or help switch that explains its use?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do all files containing scripting language code (e.g. Perl, AWK, SED, Synthesis, Scan insertion, etc) begin with a comment block describing the file, its purpose, and its revision number?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5When referring to other files of the IP, are absolute path names not used?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5When referring to files outside its own directory structure, is this done solely by environment variable?These environment variables are to be set in a single script file.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all Verification Environment configuration parameters clearly defined and located in one place?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the verification environment designed such that additional test cases can be easily added to the suite of tests?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the verification environment clearly inform you as to which test cases passed and which ones failed?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is the verification environment written in a style that defines reusable verification components (e.g. eVCs Vera, BFMs, SystemVerilog, Transactors, C++ components, etc.) that are interconnected to form the verification environment?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there one verification component written for each distinct (e.g. industry standard) interface?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Can each verification component be individually disabled by the verification environment if need be?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the Verification Environment perform protocol checking?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Can protocol errors be generated (within the bounds of the protocol)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5165Does the verification component contain monitors that look for incorrect usage or protocol violations? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5165Do the implemented checks fully cover the required protocol?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5165Can the provider show proof that all the simulation runs complete and passed at RTL level?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Can the provider show proof that the selected simulation runs complete and passed at netlist level, with and without timing annotation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has power consumption simulation been run?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has timing closure been achieved using the required constraints and with the correct margin to accommodate increased delays due to layout?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is the IP configurable?Answer yes if the IP contains parameters than can be set to configure its use for a specific application.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Are configuration examples provided?Do examples show how to configure the component at build-time for a particular customization?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2173Is the IP independent of environment variables including the $PATH variable? Answer YES if the IP refers to files in the current directory as ./filename instead of just filename.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have concurrent signal assignment statements at most one clock signal in the sensitivity list?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is any register assigned a value only from within a single concurrent process?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is simulation performance independent of the order of execution of the concurrent statements or processes?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do operand sizes match?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do mathematical operations not rely upon implicit truncation of values due to data type ranges?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have all operations involving objects of dissimilar data type either (a) appropriately overloaded operators to handle the conversion or (b) have explicit casts or type converters used to assure strict typing?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are there no disables on named blocks or tasks containing non-blocking assignments with delays?Tools handle pending scheduled values differently.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5If the IP has a programmable register set, does it have the ability to accommodate the addition of new registers in the future?Answering this question does not add or delete from the value of the IPIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is the IP designed with a building block approach with cleanly defined and functionally discrete sub-blocks?Answer YES if the IP can be updated to meet new requirements or a future update to the spec with modifications limited to as few internal sub-blocks as possible.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all interface signals defined as uni-directional even when intended for tri-state external pins?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all clock domains generated within a single clock block and then distributed to the blocks which need them?Answer YES if the clocks are generated outside of this block, or YES if this IP block has a separate clock generation sub-block at the top level of the IP deliverables that provides clock signals to the rest of the IP sub-blocks.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the system require the interaction between more than one clock domain?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Is this clock domain interaction isolated to a single block?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5187Are individual modules kept to a single synchronous clock domain where practicable? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5187Does the verification environment avoid making specific references to internal signals at the RTL level that may not be preserved after synthesis?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the IP come with a self-checking verification environment?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is the verification environment cycle-based?Cycle-based testbenches are easier to maintain and useful for generating test patterns.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2191Is a Project Schedule available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is a system requirements document available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is a design specification document available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are design specification details cross referenced to the system requirements document?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5195Is a verification specification and detailed test plan document available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are verification specification details cross referenced to the system requirements document?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5197Does the document define verification state, functional, and structural coverage targets and their achievement levels?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5197Does the functional verification documentation document the tool and platform configuration used?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5197Does the functional verification documentation document the details of the environment used for IP verification?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5197Does the functional verification documentation provide user documentation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5197Does the functional verification deliverable documentation document how to use, set up, and debug the testbench?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5197Does the functional verification deliverable documentation provide the verification steps to be performed by the IP integrator?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5197Does the functional verification deliverable documentation document how certain deliverables could be reused for system-level verification?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5197Are all stimulus source files named using a documented naming convention?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the partitioning of the IP block encourage re-use of sub-modules?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Can the architecture be readily extended when the specification is revised?This includes functional partitioning of the design blocks, available register space, the use of text macros to identify register field positions, etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Can the architecture be readily adapted to different but similar protocols?e.g. Adaptable from low speed to high speed (USB 1.1 to USB 2.0)IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is the functionality and interfaces to each module well defined?Does each module have a clearly defined purpose IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there a Requirements Traceback Matrix document that cross references the Design Specification document back to the System and Marketing Requirements documents?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the design require embedded memories?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Can the design accommodate a variety of memory suppliers?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5212Have you assured that no embedded memory is pre-loaded with other than undefined states?Defaults of X allow the verification environment to assure that it properly populates embedded memory with non-default dataIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5212Are all flip-flops reset in the same fashion (e.g. asynchronous active-low) ?All FFs in the design are reset the same way (preferably asynchronously by low active signal)IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do all bi-directional pins get set to input mode during reset?Doing so helps to avoid testing and start-up problemsIEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Do the source code files contain company copyright indications?Clear definition of ownership is essential to protect intellectual property rightsIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does each subprogram, class object or method contain an set of comments that clearly defines the functionality of the object and the purpose of each of its interface parameters?All subprograms, classes and methods should have detailed comments describing all formal parameters and the functionality of the object.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has all unused code been deleted from each file rather than being commented out within the file? Old or unused code should be deleted from each file. Version control systems should be used instead if old source code needs to be retained.IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are loops and arrays used for improved readability of the source code?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are vector operations on arrays used rather than for loops whenever possible?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Is a separate line used for each HDL statement?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Is the line length throughout consistently kept to 80 characters or less?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Is consistent use of Indentation used to improve the readability of continued code lines and nested loops?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are code constructs aligned?Are all assignment operators, declarative designators vertically aligned for ease of reading?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are case statements used rather than an if-then-else statement wherever appropriate?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are all local variables located within named blocks or subcomponents?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Do all source code files (RTL) contain a comment header that provides an overview of the file contents?A standard file header shall be used for all files. This shall contain at least: Author's name, change history log, date of creation and modificationIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all delay values passed as parameters rather than being hard coded?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Except for non-parametric signal widths, are all numeric values that represent the same item of information (e.g. register address, FSM states, etc.) defined through parameters (e.g. deferred constants or parameters)?Numeric constants shall be represented by a constant or parameterIEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are specific signal naming standards adhered to?Clock signals are readily identifiable - e.g. using prefix "clk". All clocks with the same name throughout the hierarchy should come from the same source. Scan signals are readily identifiable - e.g. using prefix "scan" Reset signals are readily identifiable - e.g. using prefix "rst" Process labels are readily identifiable - e.g. suffix "_PROC" Instance labels are readily identifiable - e.g. prefix "u_". They also bear the name of the module with a numeric suffix to differentiate. Indication of active-low signals should be consistent through-out the design, and the standard used should be given in the user documentation.IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Is the port structure standard being adhered to?Ports declared in a logical order, consistently within a given design. Ports declared one per line, preferably with a comment following it on the same line. If VHDL, always use explicit mapping for ports and generic using named association rather than positional association. If Verilog, always use explicit connection for ports using named association rather than positional association. If Verilog, always use explicit connection for ports using named association rather than positional association. Same port order followed for instantiated modules as what exists inside module. Bi-directional ports not used except when necessary to meet spec requirements.IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2When referring to common design parameters: a. Verilog: do all `define references refer to a single include file? b. VHDL: do all deferred constants obtain their values from a common package?Preference is to consolidate all references to a common placeIEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are all declarations of the same type grouped together and placed at top of each file?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Does the design utilize subprograms whenever possible rather than duplicating common code segments?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are sensitivity lists complete and without redundant signals?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is related combinational logic placed together in the same module?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all combinational modules wrapped by flip flops either on ingress or egress?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is critical path logic isolated in a separate module from non-critical path logic?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Are arithmetic equations partitioned to leverage automatic resource sharing in synthesis?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the code for sequential logic is written to infer D-type registers (flip-flops)?Technology-independent RTL style infers D-type registers for sequential logic. No latch inference in RTL, especially avoiding inferring R-S latches. Consistent coding techniques as recommended to avoid latch inference. IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Is the design Verilog?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Are non-blocking assignments always used in always @ (posedge clk) blocks for synthesis?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5242Are state machines coded to a defined standard?In Verilog, use parameter statements to define the state vector values. FSM logic and non-FSM logic separated into different modules. Assign a default state for the state machine and reset to this stateIEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Have you assured that clocks are not initialized in initial blocks?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have all internally generated clocks been bypassed while in scan mode?Answer YES if you do not have internally generated clocksIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are there are no feedback paths inside of the scan chain after scan insertion has been applied?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are multiple use pins isolated from functional logic while in scan mode?Answer YES if there are no multiple function pinsIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all hard-coded numbers, data values, or filenames represented by variables set at the top of the script?Variables used in the body of the script and their values set at the top of the script.IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Have you assured that synthesis constraints files do not define timing requirements between signals for which there is no actual connecting logic?Traditionally false paths have been used for paths for which there is no timing constraint - not that there is no physical connectivity. It is no longer true that paths that are totally asynchronous have no timing constraint - there will still be an absolute propagation delay constraint.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there a Requirements Traceback Matrix document that cross references the Test Plan Specification document back to the System and Marketing Requirements documents?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has every test case been executed without error?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does functional coverage achieve 98% for all synthesizable statements?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does toggle coverage achieve 98% for all synthesizable statements?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does line coverage achieve 100% for all synthesizable statements?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does Decision/Branch coverage achieve 100%?Each branch of a case statement or if-then-else has been exercisedIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does Finite State Machine transition coverage achieve 100%?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does expression/condition coverage achieve 98%?Have all variables of a multi-variate expression been perturbated by the test suiteIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is path coverage greater than 75%?If there are (N=two) successive conditional statements, then path coverage checking would test that all possible combinations of paths through these two successive conditional statements have been executed. (N greater than two would be ideal, but at the price of coverage execution time penalties)IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is a common routine used to display simulation messages?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does the verification environment indicate the stimulus version at run time?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Do all simulation messages indicate their point of origin?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Do all simulation messages indicate the simulation time?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do simulation messages have several levels of detail from completely silent to full information?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Do all simulation messages indicate the severity level, e.g. error, warning, note ?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is any generated data fully constrainable?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do drivers provide sufficient flexibility of configurability to indicate/inject all possible data format errors?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does the regression environment allow you to run the entire regression suite with a single script command submission. The regression environment must support running all patterns and allow the generation and re-simulation of stimulus.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the regression log file contain all information needed to reproduce the run?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are the simulation output files named consistently across simulation environments? The following files must be provided, and the following file extensions are recommended: .log - Messages generated by the regression stimulus displays, drivers, and monitor reporting; .sum - A summary log file containing results of the simulation (that is, pass or fail) and any stderr from script or simulator invocations (for example, core dumps, license unavailable, and so on).IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is the environment capable of back annotating detailed delays into models?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the regression environment provide a mechanism to backannotate delays using SDF?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does the regression environment provide a means of setting all delays to zero or unit delay?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does the verification environment include a regression test suite environment where a select list of test cases can be run at any time?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the log file contain all information needed to reproduce the run?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10274Is every single regression test able to run stand-alone?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5274Do the regression environment support running the regression suite with a single submission?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5274Are regression scripts written to be able to use Load Sharing Facilities / compute farms?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5274Have you assured that the regression tests do not rely on the results of a former regression test runIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do the simulation scripts detect simulator errors and warnings?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are errors indicated via common routines and uniform format?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Can data logging be enabled to ease debug?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is the checking mechanism automated?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Are all stimuli self-checking?Stimulus must provide a means for automated self-checking; when stimulus fails, an error must be indicated, informing the user that the test or regression has failed; all stimuli must rely on a detailed behavioral model so that the IP can check results during run time, or else the stimulus must include checking for expected results.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all errors detected at the point of failure?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Can you be assured that the environment will always produce a consistent result that is independent of the order in which the test cases are executed?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does Verification Environment indicate pass or fail at completion of simulation with an uniform format?The testbench must complete execution with a pass or fail indication; pass and fail must be mutually exclusive; if a test does not pass, it must indicate failure; time-outs are a failure; case or if statements must be complete to indicate if a test passes or fails.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is the simulation run terminated via a common routine?Errors must be indicated by common routines or mechanisms; errors must be indicated to the testbench using an error signal interface or call to a centralized error-handling task; the error-handling task must use the standard message routines (see the previous rules); drivers, monitors, and behavior checkers must flag errors using a centralized messaging- and error-handling mechanism.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does the verification environment have a means of terminating itself after a predetermined amount of time or cycles?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is hang detection or time-out mechanism provided? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the communication to drivers and monitors occur without advancing simulation time? This rule is common to drivers, monitors, and behavioral models.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the verification environment written in a style that defines reusable verification components (e.g. eVCs Vera, BFMs, SystemVerilog, Transactors, C++ components, etc.) that are interconnected to form the verification environment?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are the verification components written to avoid unnecessary event transactions (i.e. more cycle based rather than event driven) ?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5292Are the verification components extensible through language semantic inheritance?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2292Do the verification components adhere to name space avoidance guidelines?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10292Does the coding style of the verification component comply with accepted company coding guidelines or industry standards (e.g. eRM)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5292Has a standard routine been created that can reset the DUT by all possible means?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does Verification Environment check the DUT’s response to assertion/de-assertion of the resets)?There should be a test that checks the reset state of the design under testIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does Verification Environment (either within the RTL or the testbench) have the ability to generate programmable resets at times other than the beginning of the simulation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have you assured that there is only one block within the testbench used as the source of the reset function?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Can Verification Environment manage multiple resets during tests?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Can Verification Environment correctly respond to resets internally generated within the DUT?Answer YES if there are no internally generated resets.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has formal logical equivalence been run successfully between RTL and netlist representations in a representative technology?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are formal verification methods used for this design representation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nMitigable0Does the equivalence checking data provided include ALL of the appropriate data? Identification of any tools and versions used; Any scripts; Any logical constraints used; All applicable name mapping rules; Any other data needed to run logic equivalence checking between all views of the design at RTL level or below?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5304Does the transistor or gate-level equivalence checking data provided include ALL the appropriate data?Identification of any tools and versions used; Any scripts; Any other data needed to run logic equivalency checking between the RTL level design and the extracted version?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5304Does the component include appropriate scripts and data for extracting an RTL or gate-level model?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5304Does the dynamic formal verification data provided include ALL the appropriate data?Identification of any tools and versions used; List of assertions used as targets for the formal analysis; List of constraints used for the formal analysis; Identification of simulation tests amplified ; Inclusion of tests that were amplified as part of the IP verification environment?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5304Does the theorem proving data provided include ALL the appropriate data? Identification of any tools and versions used; Description of the specification model; Description of the implementation model; List of properties (relationships) proven?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5304Does the model checking or property checking data provided include the appropriate data? Identification of any tools and versions used; Environment or list of input constraints, as appropriate; List of specification properties?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5304If model checking used?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Is an assume/guarantee style of model checking supported?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2311Is model checking performed on control-intensive modules of a component? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2311Are formal methods used to generate simulation stimulus?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Is the appropriate data provided to the integrator?Identification of all tools and versions used; The set of constraints under which the stimulus have been generated; Inclusion of tests that were generated as part of the IP verification environment, etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5314Does the symbolic simulation data provided include ALL the appropriate data? Identification of any tools and versions used; The set of symbols used; The tests or testbenches used?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is VIP integration documentation available?Is a VIP Integration section available either as a stand alone document or as a chapter of the verification component User Manual?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the VIP integration documentation define the deliverables?Does this document clearly indicate the purpose of each deliverable?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10317Does the VIP vendor provide performance metrics for the VIP?For example simulation loadIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2317Does the VIP support accelerator/emulators?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0317Does the vendor provide information of capacity / utilization for the VIP?Answer "n" if acceleration and emulation is not supported.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2320Does the documentation fully define the interfaces to the VIP?Does this document provide a definition of all interfaces, their function and any interface requirements?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10317Are all the VIP configuration parameters described?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10317Are typical and useful integration case examples available?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5317Are requirements and recommendations provided for the verification plan, strategy, and/or testbench infrastructure that maximize the VIP benefits and promote reuse across verification stages and projects?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2317Are all requirements related to the VIP's operation documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5317Are all requirements related to the testbench using the VIP documented? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5317Are reset, initialization, enable, and disable methods described ?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10317Does the integration documentation include a tutorial of the VIP's use?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5317Is a detailed VIP specification document or chapter available ?Is a VIP specification section available either as a stand alone document or as a chapter of the verification component User Manual?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is there a reference section that list all the documents that the VIP was based on?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5330Are all the features supported by the VIP cross-referenced to the interface specification?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2331Are the interface features not covered by the VIP well documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10330Are all the supported events and/or transactions described?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5330Is all the supported checking described?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5330Are all the supported coverage features described?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5330Are the supported levels of abstraction and accuracy well documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5330Are any relevant timing interactions well documented?For example time consumptionIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10330Is a block diagram, class diagram or other appropriate architectural description available?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5330Is each of the major components of the VIP described?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5330Are known, unresolved and outstanding issue described?Does the document indicate all unresolved issues? Answer YES if there are no unresolved issues or if this is the first release.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the VIP configurable?Answer yes if the VIP contains parameters than can be set to configure its use for a specific application.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have all the advertised configurations been covered by the validation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5342Does the validation plan clearly describe any configurations that have not been covered?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10342Is the VIP parameterizable to enable reuse of the model in a variety of testbench setups?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5342Is there a mechanism provided to verify correct installation of the VIP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the VIP installation self-contained?“Self-contained” means that the VIP installation package is free of dependencies on libraries or VIP that are not included in the package. IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do you take advantage of industry standard compliance testing if applicable and available?System protocol compliance verification verifies that the IP complies to the industry standard protocol supported by the IP (e.g. USB2.0).IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has the IP passed the industry standard compliance certification testing?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5348Does the VIP not use hard coded pathnames; but only relative pathnames or pathnames relative to a root defined by an environment variable?For any internal or external tool, script or file required to use the VIP there must be a clearly documented method to identify and eventually modify the appropriate location in the actual environment.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the VIP include a documented set of methods and/or wrappers for the language environments for which it claims support?For example, for a Verilog based VIP to support VHDL it must be provided with a VHDL language wrapper.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Has the VIP been proven compatible with an industry-wide verification methodology such as AVM, URM, or VMM?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Can each verification component be used with different configurations for each instance in the environment if need be?The single monitor may encapsulate multiple modules or monitors as required.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does training for the IP exist?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2If source code is not available, can all relevant aspects of inner workings of the model be viewed and controlled directly?Answer YES if the source code is provided as a deliverable or if the VIP source code can be purchased or licensed.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has a product brief been developed (e.g., 2-3 page datasheet)?Answer YES if the Product Brief has been developed and is available for customer use.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Can a validation test plan document be made available? Is there a document which describes the environment and test cases used to prove that the verification IP works as intended?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is the validation plan cross referenced to the relevant functional specifications?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5357Is there a standard compliance test available?The corresponding standard and compliance check should be identified in the comments column.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0357Is the test part of the validation plan?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5359Do the quality check deliverables include verifying error conditions?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10357Are verification specifications cross-referenced to the System Requirements document?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the VIP a driver or a responder?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Is the driver independent of any checks or monitoring capabilities?Checks and monitors should be reusable at higher level of DUV integration, even when the drivers are not applicable.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5363Does the driver provide error injection capabilities?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5363Is a method to control the distribution of errors available?Protocol errors should be within the bounds of the protocols.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2365Does the driver allow the user to control the values assigned to the interface?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5363Is the VIP a monitor?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Are all portions of the specified interface protocol supported by the VIP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5368Is the monitor passive?A monitor should only include checking and/or trace log features. It should not affect the operation of a device.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5368Does the monitor operate on one interface only?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5368Does the monitor provide a method to control the checks performed on the interface?Should be able to turn off or modify severity of results of checks.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5368Does the monitor allow the user to access the states of the various checks?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2368Does the monitor provide a control to disable, enable, or hold the checking?Useful when testing error recovery scenariosIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5368Does the monitor recover from bad stimuli?Error conditions are often used in testing to verify proper DUV response, they should not confuse the monitor which is meant to verify that the DUV is operating correctly.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2368Can the monitor provide a trace of bus activity for use in debugging?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5368Can the monitor be used with formal verification?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0368Can the monitor be used to constrain formal verification?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2377Do the checkers provided with the monitor support the Assume-Guarantee Reasoning verification methodology?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2377Can formal tools safely assume 0 or 1 values for X or Z values without the use of 4-state semantics?If the assumption cannot be made 4-state formal tools is required. 2-state semantics 0, 1 (or L, H) 4-state semantics X, Z, 0, 1 (or L, H)IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2377Are all checks implemented in the monitor written as safety checks?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2377Can formal proofs be performed with tools not supporting liveness?liveness support requirements limit the tools that can be used with the VIPIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2377Does the monitor provide timing checks on the protocol?For example relationship (A comes before B). A and B could be transactions, signals etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2368Can the monitor be used for timing checks in gate-level simulation?For example setup/hold, etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2368Can each individual coverage metric and statistic for optional protocol features be enabled and disabled?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5368Is the VIP a bus functional model (BFM)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Does the BFM implement full interface functionality?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5386Can the BFM be used as a reference model in gate-level simulation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2386Does the VIP support stimuli generation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all portions of the specified interface's full protocol supported by the VIP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5389Can the generation be controlled by the verification environment?For example, is it possible to disable or modify specific scenario's IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10389Can all possible sequences for the VIP be generated?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5389Is random stimuli generation available?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5389Can randomization be controlled by seeds set by the verification environment for each individual VIP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5389Is the randomization capability independent of platform or tools?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5389Can the generator reliably regenerate a specific scenario?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10389Does the VIP come with an integrated suite of test cases?Often directed tests to test basic functionality of the VIP as well as for integration purposes.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Do the test cases target sanity case tests?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2397Do the test cases target manufacturing tests?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2397Is there a simple example on how to model a test case?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2397Are standard traffic stream tests provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5397Are clear instructions on how to create new tests available?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5397Can the test suite leverage multiple generators ?DUV as well as modelIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5397Does the integration suite of test cases support reuse in other environments?For example, test suites used in simulation be reused with emulationIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2397Can the test suite be extended with user-defined tests?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5397Are templates of standard traffic elements (e.g., packet types) provided for user-created tests?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5397Does the VIP come with an integrated suite of compliance cases?Often directed tests to test basic functionality of the VIP as well as for integration purposes.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is each compliance test case cross-referenced to the relevant areas of the specification?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2407Are conditions which the test must drive the DUV to a specified DUV state clearly documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2407Are test sequences documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2407Are there tests for every major area of the specification?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10407Do the compliance test cases target standard compliance tests?Is the compliance test suite from a standard organization, which version of specification does the test suite conform to?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2407Do the compliance test cases target corner case tests?The VIP should have difficult to reach scenarios and what sequences are required to attain them, cross referenced to relevant areas in the specification.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2407Do the compliance test cases target sanity case tests?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2407Do the test cases leverage randomization?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2407Are seeds handled so they can be easily used to replay test runs?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5415Are coverage metrics available to evaluate completeness?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5407Is a DUV-side driver mechanism provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5407Does the compliance suite of test cases support reuse in other environments?For example, test suites used in simulation be reused with emulationIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2407Are all required components supplied with the test suite?All components required by the test suite to functioning should be part of the delivery.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5407Can the VIP be used at different levels of DUV integration?Checks and monitor should be reusable at any level of DUV integration. Drivers and result checkers should be reusable when DUV interfaces are also interfaces at higher level of integration.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the VIP support self-checking capabilities?A scoreboard or other test bench component that does self checking requires information from the VIP to compare with the activity on the DUV side. This includes transaction properties, responses, data, special events such as reset, etc. The VIP should provide such information to enable the implementation of self-checking capabilitiesIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the VIP provide means for the environment to control and observe the activity and state of the VIP?VIP provided in compiled form must provide alternative capabilities for debug and traceability, access for the environment to probe if a transaction has started, ended etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is the VIP partitioned for reuse?Partitioning is important for reuse throughout the full verification flow including for prototyping, such as having separate verification components (drivers, monitors, slaves, generators), and control and coverage collectors?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the VIP provide information to allow the testbench to capture protocol related coverage?The information should include all protocol related activities.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the VIP provide pre-defined functional coverage for the interface it supports?The VIP should provide some basic functional coverage capabilitiesIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Can functional coverage be extended by the testbench?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5426Can functional coverage be completely disabled?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5426Can the coverage be easily integrated with the user-defined coverage in the testbench?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5426Does the VIP provide means for the verification environment to access traffic information?The traffic information must include all data and protocol relevant control information such as delays, response types and can be used by the environment to build scoreboards etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the VIP come with simulation-time metrics to validate performance?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Are any batch regression usage issues documented?Examples would include shared files or fixed input or output file names that interfere with simultaneous simulation runs, license issues, excessive output/file size limitations.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the VIP include checkers to help verify whether the VIP is integrated correctly?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does the VIP include checkers to warn of untested and/or invalid configurations and parameter ranges?The VIP should provide reporting of which configurations and ranges that was not covered during the verification tasks. IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Can the VIP or part of the VIP be used with formal verification?The VIP should provide information on tool name, version and potential limitations.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Are constraints written for compatibility with both formal verification and simulation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5435Can the constraints be used as assertions or easily converted into assertions when integrated with other blocks?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5435Can the VIP or part of the VIP be used with hardware accelerators and/or emulators?The VIP should provide information on supported emulation/acceleration systems, supported versions, and potential limitations.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is VIP revision information written to the environment when the VIP is in use?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are messaging and reporting formats controllable and customizable?Can reporting methods be replaced with environment specific methods and do they include the full instance path names for the reporting instance.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the VIP indicate pass or fail at completion of the simulation using a uniform format?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are failure indications from the VIP easy to post-process to determine pass/fail status?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is there an IP Integration Manual or Chapter available?If Integration manual does not exist, then do not answer remaining questions in this sectionIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the IP integration section define the deliverables?Does this document clearly indicate the purpose of each deliverable?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10443Does the document fully define the interfaces to the IP?For each interface object, provide details including: - Interface name - Purpose - Description & characteristics (e.g. for software, Input parms/argument description(s) & return parm description(s) - Dependencies/assumptionsIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10443Does the document define naming conventions?Does this document define the naming convention used within the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5443Is there a means of verifying the completeness of the deliverables?Does this document contain a section that clearly shows you how to set up and verify that you received a complete and working IP block?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5443Does the document describe how to instantiate the IP component?Provides information regarding how to install and build component including: - Host environment (Unix, Windows) - Directory structure - Installation procedure - Installation validation - Tools used to build component (w/version numbers) - Configuration - How to verify successful installationIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5443Does the document describe how to create tests?Information regarding how to test integrated Component, how to build self-test, etc. Subsections include: - Introduction - Test characteristics (platform/testbench, etc.) - Test architecture - Self test installation/construction - Self-test description(s) IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5443Does the document provide instructions for how to build an environment using this component?Does this document include a chapter that describes the simulation and setup scripts, the tool chain used and how to build the standalone testbench?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5443Is an IP reference manual available?Does the IP contain a hardware reference manual or datasheet?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the document contain a functional description of the IP?Does the documentation describe the overall scope and purpose of the software?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10451Does the document contain an Architectural Overview?Provides high level architectural block diagram from integartors perspective (I.e. shows component as a "black box" with all interfaces clearly labeled). Further, provides breif description of each interface with a narrative regarding component's functionalityIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10451Does the document describe all available features?Provides detailed information regarding component's characteristics such as dependenciesIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10451Does the document fully define the interfaces to the verification IP?Does the document include a detailed definition of all interface objects, their datatypes and, if applicable, data flow direction?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10451Does the document contain a section regarding object types?Does the document clearly define all of the available object definitions?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10451Does the document contain a section regarding procedure calls, interupts and exceptions?Is there a section that describes how subprogram calls, exceptions and interrupts are handled?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10451Does the document contain a section regarding input/output processing?Is there a section that defines all of the I/O possibilites and how to program each?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10451Are there release notes available?Does the IP contain a release notes document?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are enhancements and improvements described?Does the document define new features & enhancements by revisions number?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5459Are bug fixes described by the revision notes?Does the document indicate enhancements relative to previous releases?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5459Are known, unresolved and outstanding issue described?Does the document indicate fixed errors and omissions from previous releases?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5459Is the IP configurable?Can the IP be configured to suit the application or target platform?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Does the IP have structured and consistent static (build-time) and/or dynamic (run-time) configuration capabilities?Level of component's configurability including: - Are all configuration variables explicitly defined with no redundant or overlapping variables - Are hierarchies obvious with higher level variables "controlling" lower level variables - Are all static configuration variables defined on compiler/assembler command line, defined in an input file to compiler/assembler, defined in a single include/header file (i.e. not declared/defined using multiple methods unless required and intuitive)IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5463Well organized (limited number of files, files have single purpose)Level that component's files are organized i.e. are there a limited number of files with some description and sense of organization, build/link order, etc. If any files require modification in order to integrate component, are such files well defined.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5463Are configuration variables or variables clearly defined?Level that component's configuration variables are defined i.e. is each variable well defined with description of valid values and resultant effect on buildIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5463Are configuration examples provided?Do examples show how to configure the component at build-time for a particular customisation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2463Is software configuration management in place to support different build types such as Release, Debug?Answer yes if this capability exists and is reasonably easy to accomplish.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2463Is the order of file compilation clearly documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the IP include a MAKE file or other means of installation or compilation?IP blocks are frequently comprised of a set of files that need to be compiled in a specified order. IP providers are encouraged to simplify this compilation by providing their customers with compilation scripts that automate this process. Enter YES if this IP block is delivered with a script, MAKE file or other means of automatic compilation.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the IP have a documented and well ordered directory structure?How straight forward is directory structure? How easy is it to incorporate component's directory structure with structure of product being developed? IP has a well organized directory structure. IP directories have a ReadMe file that explain the function of files in that directory. IP files follow some naming convention that makes it easy to understand the function of the files. An example is name_type.ext where type and ext are used to classify files. Example do_synth.cmd, sss_monitor.v, etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Will the build environment automatically create any of the directories or intermediate working files it needs as part of the build process?Answer YES if, other than setting up the root directory, the build environment will automatically handle the creation of the sub-directory trees that it requires.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is documentation available that informs you of the tools (revision levels, variants, etc.) used to develop this component?Are the tools used to develop the component clearly defined including revision levels, variants, etc. Is this compatible with the rules used in the integration environment? Are configuration parameters that require to be applied to the tool described?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have module name-space collisions been avoided by adopting a non-interfering naming convention?Does the IP have a distinct prefix or suffix that helps to avoid name space collisions?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Except for the top-most level, are all file pathnames relative?You should answer NO to this question if the IP refers to absolute path names to a specific directory rather than relative pathnames to the root of the IP design tree.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all required files included within the IP delivery?The IP integrator should not be required to locate or download files from other sources in order to integrate an IP block into and SoC design.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is the IP independent of environment variables including the $PATH variable? Answer YES if the IP refers to files in the current directory as ./file_name instead of just file_name.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Other than tool dependent configuration files, is the IP designed to be tool independent?Answer NO if the IP relies upon vendor specific language extensions or environments.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does training for the IP exist?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the IP source code provided?Answer YES if the source code is provided as a deliverable or if the IP source code can be purchased or licensed.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the IP designed with a building block approach with cleanly defined and functionally discrete sub-blocks?Answer YES if the IP can be updated to meet new requirements or a future update to the spec with modifications limited to as few internal sub-blocks as possible.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is an application programming interface (API) library required for this IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Is the API provided with the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10482Is the API fully documented?Is the use of the API clear and well defined?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10482Does the IP come with a self-checking verification environment?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the documentation clearly describe how to set up this environment and run through the self-test diagnostics?Using the provided documentation, setup the environment and run the tests. If the procedure is clear, answer YES, otherwise if the procedure requires you to contact the supplier in any manner or if there is no documentation, then enter NO.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10485Are the test reports/results clearConsidering the test environment, how clear are the test results? Is there documentation describing how to interpret the test results e.g. if terse results provided (such as a light blinking or a result number displayed) is there documentation regarding the meaning of such indications? If display strings or log files are used is there documentation describing the strings or messages?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10485Are expected discrepancies documented and explained?Discrepancies may occur due to synchronization or X-propagation. These should be documented.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5485Has a Product Brief (e.g. short 2-3 pg datasheet) been developed?Answer YES if the Product Brief has been developed and is available for customer use.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Does the document adhere to company templates?Answer Yes if it adheres to company adopted standard templates.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5489Is a Project Schedule available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the document adhere to company templates?Answer Yes if it adheres to company adopted standard templates.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5491Is a system requirements document available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the document adhere to company templates?Answer Yes if it adheres to company adopted standard templates.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5493Is a design specification document available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are design specification details cross referenced to the system requirements document?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5495Does the document adhere to company templates?Answer Yes if it adheres to company adopted standard templates.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5495Is a verification specification and detailed testplan document available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are verification specification details cross referenced to the system requirements document?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5498Do the documents adhere to company templates?Answer Yes if it adheres to company adopted standard templates.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5498Are quality audits and checklists available other than this QIP?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Do the documents adhere to company templates?Answer Yes if it adheres to company adopted standard templates.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5501Are Requirements cross referenced to the design spec?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5The partitioning of the IP block encourages re-use of submodulesIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the functionality and interfaces to each module well defined?Does each module have a clearly defined purpose IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is the code self-initializing?Self-initializing code is software that initailzes all global veriables such that program can be restarted (NOT power down/restart) and software will dynamically establish initial state of system. Another view is that at start up software makes no assumptions about system's state and initializes hardware, all global variables, tables, etc. during initializationIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are all variables explicitly assigned default values?All objects shall be assigned default values and not rely upon the compiler to do this on your behalf.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is the operation of the module predictable when the reset is removed?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Does the source code files contain company copyright indications?Clear definition of ownership is essential to protect intellectual property rightsIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Do all source code files contain a comment header that provides an overview of the file contents?A standard file header shall be used for all files. This shall contain at least: Author's name, change history log, date of creation and modificationIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does each subprogram, class object or method contain an set of comments that clearly defines the functionality of the object and the purpose of each of its interface parameters?All subprograms, classes and methods should have detailed comments desribing all formal parameters and the functionality of the object.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Except for non-parametric signal widths, are all numeric values that represent the same item of information (e.g. register address, FSM states, etc.) defined through parameters (e.g. deferred constants or parameters)?Numeric constants shall be represented by a constant or parameterIEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Has all unused code been deleted from each file rather than being commented out within the file? Old or unused code should be deleted from each file. Version control systems should be used instead if old source code needs to be retained.IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are all declarations of the same type grouped together and placed at top of each file?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Does the design utilize subprograms whenever possible rather than duplicating common code segments?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are loops and arrays used for improved readability of the source code?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Is a separate line used for each statement?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Is the line length throughout consistently kept to 80 characters or less?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Is consistent use of Indentation used to improve the readability of continued code lines and nested loops?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are code constructs aligned?Are all assignment operators, declarative designators vertically aligned for ease of reading?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are general naming standards followed?Documented naming conventions used consistently throughout the design. Names used in source code match names used in design documentation, and these are short and meaningful. Lowercase letters for all signal names, variable names, and port names. Uppercase letters for names of constants and user-defined types. Characters used only from the set [a-z,A-Z,0-9,_] in all names; all names begin with a letter. Maximum name size is 32 characters and minimum name size is 3 characters. Names are not reused for different classes of identifier, and do not use case to differentiate identifiers (e.g. clk vs. Clk)IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are case statements used rather than an if-then-else statement wherever appropriate?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Has an automatic and/or manual audit of the design been conducted and an audit report made available?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do all interface objects (module names, components, formal parameters, etc) have names that are unique and avoid system level name space collisions?It is essential to avoid name-space collisionsIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Are all interfaces and each of their formal parameters clearly defined?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are specific interface naming standards adhered to?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are external interfaces to hardware and software defined?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the design utilize subprograms whenever possible rather than duplicating common code segments?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do all files containing scripting language code (e.g. Perl, AWK, SED, Synthesis, Scan insertion, etc) begin with a comment block describing the file, its purpose, and its revision number?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does each executable script contain a "-h" or help switch that explains its use?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all hard-coded numbers, data values, or filenames represented by variables set at the top of the script?Variables used in the body of the script and their values set at the top of the script.IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2When referring to other files of the IP, have you assured that absolute path names not used?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5When referring to files outside its own directory structure, is this done solely by environment variable?These environment variables are to be set in a single script file.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have you assured that there are no hard-coded numbers, data values, or filenames buried in the body of the script? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are abstraction layers required?Depending on nature/purpose of component, are abstraction layers required to isolate unique aspects of integration. Examples of abstraction layers include: host interface, hardware or I/O interface, OS/kernel interface, etc. NOTE: this question asks if Abstraction is required, NOT does component have an abstraction layer.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0If required, do abstraction layers exist?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5535Is abstraction layer kept minimal and easy to understand and implement?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5535Is there a detailed description for each API?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5535Is there a prototype provided for each API?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5535Is are API Inputs defined?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5535Is are API outputs (return parameters) defined?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5535Is Portability a requirement of the component?Depending on nature/purpose of component, is portability required i.e. is it required that component be processor or platform agnostic? NOTE: this questions asks if Portability is required NOT is component portable.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Are all pprocessor independent constructs defined?Are processor constructs (endianess, word size, etc.) clearly defined and modifiableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5542Is each construct well defined?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5542Are real time and performance requirements clearly stated?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does component use dynamic fault checking?In Test Configuration, does component check for logic errors in both Test configuration and possibly run-time configuration e.g. null pointer checks, stack ofl/underflow, check for illogical variable values and "trap" or log if discovered, etc. IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does component have logging & trace capabilities?Is information regarding how to capture logging, trace and self-check errors defined?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is component's method of communicating self test errors documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the achitecture cross referenced to the system requirements?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the software architecture for the component described within context to the overal system perspective? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has the architecture decomposed the system into reusable subcomponents and managable blocks?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all relationships & interfaces identified?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all data structures and/or tables identified?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are design details cross referenced to the architecture and systems requirements?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have real-time factors been given consideration and documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have critical sections been identified and documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there a definition of the start up/initialization sequence including considerations for power-on-self-test?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the motivation & purpose of module/object documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all modules well defined in terms of functionality and interface to other modules?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the API defined and fully documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the functionality of the modules is focused and reasonably orthogonal to alternative module functionality?Does each module have a clearly defined purpose that is summarized in one sentence (i.e. it does only one thing and does it well).IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have you assured adherence to Reuse Coding Standards across all files?Does source code adhere to Reuse Style & Coding guidelines. Or, if it does not follow standard, does it follow some standard?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are file name conventions consistent and follows architectural & design blocks (Data & code source file partitioning relates to architecture & design)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does each file contain a commented prolog describing the file's purpose, author and revision history?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there a commented prolog at start of every data structure definition?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there a commented prolog at the start of every module/function/block?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are comments used throughout all files explaining purpose and/or functionality of all data structures, functions, modules, and blocks of code?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all values/constants symbolically defined?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are all identifier names "meaningful" and follow a naming convention?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have you assured that data types are not dependent on language implementation details?If a type can be implemented as multiple widths (e.g., int in C), don't use it directly when width is important. Ditto for possibly-unsigned types (e.g., char in C) if signed-ness is important. Use more specific alternatives (e.g., int32_t, uint8_t), or define project-specific types if needed.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have you assured that data operations are not dependent on language implementation details?For example, in C/C++, bitwise operations must not be used on signed integers, and the internal representation of floating point numbers must not be accessed directly. In cases where dependencies cannot be avoided (e.g., signed integer division in C), they must be well documented.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have you assured that each global construct is only declared once?Global constructs include macros, type definitions, global variables, etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have you assured that global construct names are not reused with different meanings?Global constructs include macros, type definitions, global variables, etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is the design coded primarily in a portable langage for which there is a well-defined standard?For example, ANSI CIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nMitigable0Have you assured that the implementation uses only standard constructs?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5574Is the use of language extensions well documented?Includes standard extensions (e.g., #pragmas) as well as non-standard ones. Check y if no extensions are used.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5574Are file names and their contents related?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are contents organized consistently( e.g. similar objects, variables, symbols, etc. grouped together in same header)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are header files self-including?Self-checking headers have a condifional compilation at the start of the file checking if header was previously referenced (included) and, if so, header is not compilied again. This avoids situation of a header being included in other headers and being compilied multiple times resulting in many syntax errors. For example, C headers self-check by using '#ifndef/#define/#endif' mechanism to prevent multiple inclusions as seen below: #ifndef head_name #define header_name header source code goes here - within scope of #ifndef #endifIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there a separate line used for each declared variable, symbol, etc.?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are line length kept to a consistent limit?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Are macros declarations documented (commented) and simple to understand?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are the names of file names and the contents of those files related to one another?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are contents organized consistently ( e.g. similar functions, modules, blocks of code, etc. grouped together in same file)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Have you limited coding to one statement/instruction per line?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are line length kept to a consistent limit?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is consistent indentation used?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are header Files referenced at beginning of each file?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are the global declarations declared at beginning of files?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the code make logical/judicial use of macros, equates, and aliases?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is the initialization code clearly delineated (I.e. can easily locate/identify code start)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Do functions or block interfaces include "active" boundary checks (i.e. do functions or interfaces return errors indicating parameters exceed legal values)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are multiple configurations supported (e.g. Test configuration, Production ("run-time") configuration, etc.)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are configurations well commented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is this firmware IP for an embedded system with real-time constraints?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Has real time perfomance been tested/verified/documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10595Does line coverage achieve 100% for all statements?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does Decision/Branch coverage achieve 100%?Each branch of a case statement or if-then-else has been exercisedIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does FSM state transition coverage achieve 100%?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does expression/condition coverage achieve 100%?Have all variables of a multi-variate expression been purturbated by the test suiteIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is path coverage greater than 75%?If there are (N=two) successive conditional statements, then path coverage checking would test that all possible combinations of paths through these two successive conditional statements have been executed. (N greater than two would be ideal, but at the price of coverage execution time penalties)IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has every test case been executed and yield the expected response?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Has a syntax-checking tool (e.g., LINT) been run on all source files?Or, if the project coding guidelines refer to specific syntax checking tools, have they been used consistently?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Do all source files compile without warnings?Or if some warnings are inevitable, they must be extremely well-documented.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is a common routine used to display simulation message?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Do all messages indicate their point of origin?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Do messages indicate their severity level (e.g. error, warning, note )?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Is the verification environment designed such that additional testcases can be easily added to the suite of tests?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Does the verification environment include a regression test suite environment where a select list of testcases can be run at any time?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is every single regression test able to run stand-alone?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5609Do the regression environment support running the regression suite with a single submission?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5609Does the log file contain all information needed to reproduce the run?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10609Does the verification environment clearly inform you as to which testcases passed and which ones failed?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Can you be assured that the environment will always produce a consistent result that is independent of the order in which the testcases are executed?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Is the test coverage documented ( i.e. degree at which software component's logic is exercised/tested)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there a sufficient level of stress testing in verification software?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there a sufficient level of boundary (corner case) testing in verification software?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is there a sufficient level of "negative" testing in verification software?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Is "free-running" regression testing considered (with check pointing, logging, elapsed time and other statistics)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Are random test case generated?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledHas the Si Tapeout Development phase for this IP been completed?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledHas the Si Characterization phase for this IP been completed?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledHas this IP been in product production?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes training for the IP exist?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryDupEnabledDo you take advantage of industry standard compliance testing if applicable and available?System protocol compliance verification verifies that the IP complies to the industry standard protocol supported by the IP (e.g. USB2.0). Answer 'y' if not applicable.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryDupEnabledHas the IP passed the industry standard compliance certification testing?Answer 'y' if not applicable.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5625DigitalAnalog/AMSI/O and ESDMemoryMEMSIs an IP Integration manual or chapter available?Does the IP contain an integration manual or integration application noteIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the IP integration section define the deliverables?Does this document clearly indicate the purpose of each deliverable?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10627DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the document fully define the interfaces to the IP?Does this document provide a definition of all interfaces, their function & electrical characteristics and any interface requirements?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10627DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the document define naming conventions?Does this document define the naming convention used within the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5627DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the document describe how to instantiate the IP component?Provides you with an SoC integration instantiation template and shows you how to connect the block to the rest of the SoC?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5627DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the document provide floorplanning guidelines?Document should indicate layout restrictions, guard rings, separation rules, isolated power requirements, trim circuits.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5627DigitalAnalog/AMSMemoryMEMSDoes the document detail the System Level Model usage?Document should show you how to use the delivered system level model.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2627DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the document provide instructions for how to build an simulation/test environment using this component?Does this document include information that describes the simulation and setup scripts, the tool chain used and how to build the standalone testbench? Does this document include information that describes the timing validation and manufacturing tests and environments?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5627DigitalAnalog/AMSI/O and ESDMemoryMEMSIs there a documented tool compatibility list?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2627DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the document provide technology information, area and power?Does this document contain a section that describes a sample technology library and the expected performance characteristics of an implementation in terms of power and area given that technology?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10627DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the design specification cover operating environment requirements (ambient temperature, radhard, etc)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5627DigitalAnalog/AMSI/O and ESDMemoryMEMSAre the voltage levels and voltage tolerances clearly documented for each supply voltage?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10627DigitalAnalog/AMSI/O and ESDMemoryMEMSAre any noise requirements or supply isolation requirements clearly documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5627DigitalAnalog/AMSI/O and ESDMemoryMEMSAre the supply impedance requirements for the package and board design clearly documented for these isolated supplies?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5627DigitalAnalog/AMSMemoryMEMSAre any supplies connected to the rest of the chip?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryMEMSAre ways to connect these common supplies to the chip power grid clearly documented for different IP orientations?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5641DigitalAnalog/AMSMemoryMEMSAre any requirements placed on the chip power grid clearly documented (noise, de-coupling, impedance)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryMEMSIs there a requirement in the IP for multiple power domains?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryMEMSAre the power supply sequencing requirements clearly documented for the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10644DigitalAnalog/AMSMemoryMEMSDo any of the power supplies require a Kelvin connection to the supply ring?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryMEMSIs the Kelvin connection clearly documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5646DigitalAnalog/AMSMemoryMEMSDo any of the IP power supplies have a special stand-by requirement like a battery or capacitor back up?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryMEMSIs the special power requirement clearly documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5648DigitalAnalog/AMSI/O and ESDMemoryMEMSIs there a means of verifying the completeness of the deliverables?Does this document contain a section that clearly shows you how to set up and verify that you received a complete and working IP block?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSIs a LEF description of the macro provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSIs a GDSII Stream layer mapping file provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the IP block include a lib pin timing file?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSDoes the IP block include a Bus Functional model?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSMemoryMEMSDoes the IP block include a behavioral model?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledIf the IP has been verified in silicon, is a characterization report available?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledDoes the report describe the IP performance over process, voltage and temperature?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10656DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledDoes the report compare measured silicon performance versus the simulations across PVT?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2656DigitalAnalog/AMSMemoryMEMSDupEnabledDoes the report detail power dissipation and power management strategies?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5656DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledDoes the report thoroughly describe the characterization testing procedure?This includes test strategy and test coverage, wafer tests, package tests, lab functional, characterization, and debug tests, and ESD testing. Detail tests and or deviations in the comment column.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5656DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledAre all the failures / deviations analyzed with root causes documented? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10656DigitalAnalog/AMSI/O and ESDMemoryMEMSIs there a test plan document included with the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the test plan include recommended test order and flow for all conditions (wafer sort, burn-in, package test, etc)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2662DigitalAnalog/AMSMemoryMEMSAre ATPG test vectors supplied with the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSHave DFT techniques been implemented and documented for the hard macro?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSCan the tests be performed without any special test hardware requirements? If not, please comment on hardware needed.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledIf the IP has been validated in silicon, is a test chip report available?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledDoes the document contain a description of the test chip?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10667DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledDoes the document describe the hardware test environment, test equipment, and test setup used?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5667DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledDoes the document detail the boundary temperatures at which the silicon was validated?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10667DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledAre the items not tested documented (assumed correct by design)?List any untested items in the comment section.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10667DigitalAnalog/AMSMemoryMEMSDupEnabledHas the IP has been verified and documented for plug and play interoperability versus the specifications?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSDupEnabledDoes the interoperability document detail whether the IP meets the industry standard spec (e.g. Jedec)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10672DigitalAnalog/AMSDupEnabledDoes the interoperability document detail whether the IP 100% passed a certification test?schIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10672DigitalAnalog/AMSMemoryMEMSDupEnabledDoes the interoperability document detail any waivers given at the certification test?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10672DigitalAnalog/AMSMemoryDupEnabledDoes the interoperability document detail the interoperability tests?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10672DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledAre there release notes available?Does the IP contain a release notes document?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledAre enhancements and improvements described?Does the document define new features & enhancements by revisions number?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5677DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledAre bug fixes described by the revision notes?Does the document indicate fixed errors and omissions from previous releases?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5677DigitalAnalog/AMSI/O and ESDMemoryMEMSDupEnabledAre known, unresolved and outstanding issue described?Does the document indicate all unresolved issues? Answer yes if there are no unresolved issues.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10677DigitalAnalog/AMSMemoryIs the IP configurable?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryAre configuration examples provided?Do examples show how to configure the component at build-time for a particular customization?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2681DigitalAnalog/AMSMemoryIs the design scalable? (e.g. 2 channel, 4 channel, etc)Is it easy to install the component for a number of different build-time configurations? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryIs the scalability described in the IP Integration Manual?Is it easy to install the component for a number of different build-time configurations? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10683DigitalAnalog/AMSMemoryDoes the IP include a MAKE file or other means of installation or compilation?IP blocks are frequently comprised of a set of files that need to be compiled in a specified order. IP providers are encouraged to simplify this compilation by providing their customers with compilation scripts that automate this process. Enter YES if this IP block is delivered with a script, MAKE file or other means of automatic compilation.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the IP have a documented and well ordered directory structure?How straight forward is directory structure? How easy is it to incorporate component's directory structure with structure of product being developed? IP has a well organized directory structure. IP directories have a ReadMe file that explain the function of files in that directory. IP files follow some naming convention that makes it easy to understand the function of the files. An example is name_type.ext where type and ext are used to classify files. Example do_synth.cmd, sss_monitor.v, etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSIs a complete physical implementation of the macro provided in GDSII?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSIs a LEF description of the macro provided?Details macro pins and their locations, macro size, system routing constraints over and around the macro. It should include text markers identifying each pin and the polygonal boundary of the macroIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSIs a GDSII Stream layer mapping file provided?The mapping file maps GDSII layers onto mask layersIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSI/O and ESDMEMSAre full schematics of the IP provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSAre any additional well or substrate protection required outside the macro described?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryIs there a model available at a suitable level of abstraction to enable system level evaluation?Answer YES if a Verilog AMS model is available.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSMEMSIs a Verilog AMS or VHDL AMS model provided?Answer YES if the source code is provided as a deliverable or if the IP source code can be purchased or licensed.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Analog/AMSIs a Matlab or equivalent system level model provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSMemoryMEMSAre models containing full descriptions of the electrical characteristics of the macro ports provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSTo enable accurate simulation of the macro in the system, is a mixed-level simulation model provided containing behavioral models of non-critical sub-blocks and circuit level representation of critical sub-blocks?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSIs the functionality of each interface clearly defined?Answer YES if each interface is clearly defined and you can readily understand how to design logic to support the interface definitions.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSDoes the IP connect to a fully documented industry standard interface?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSIs the IP's interface fully compliant with this standard?Answer NO if the IP is not fully and 100% compliantIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10698DigitalAnalog/AMSMemoryMEMSDoes the IP design has a detailed set-up, valid and hold timing specification for all interface signals?It is good practice that the IP registers all inputs and outputs so that internal IP timing closure is isolated from the outside timing closure issues. However this may impose an unacceptable penalty in terms of power, area, latency or data throughput, and may indeed violate the specification. All interfaces shall specify their timings (soft IP) or library timings (hard IP)IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryMEMSDoes the timing view define the max transition for input and inout pins?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSDoes the timing view define the max capacitance for output and inout pins?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSDoes the max capacitance value reflect the size of the characterization table?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSDoes the max transition value reflect the size of the characterization table?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSIs the max transition delay appropriately sized for the technology?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSIs the max capacitance value appropriately sized for the technology?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSIs the input and inout pin capacitance correct with respect to the spice netlist?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryMEMSDo the timing arcs have negative slopes?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSMemoryMEMSDo the cell intrinsic delay values monotonically increase with increasing load capacitance or input ramps?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSMemoryMEMSDo the cell output transition delay value monotonically increase with increasing load capacitance or input ramps?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSMemoryMEMSDoes the IP interface with a standard on-chip bus or is the interface generic enough to be easily interfaced to standard on-chip buses?Answer YES if the IP can be easily integrated into an SoC from an interface perspectiveIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryAre power supplies used by this IP completely isolated from the other supplies on-chip?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryAre all isolated power supply planes required on the board documented for this IP?List the number of isolated planes required and their names in the comment section.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10712DigitalAnalog/AMSMemoryCan any IP supplies be routed without planes as signal traces on the PC board?List these supplies in the comment section.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the IP come with a comprehensive verification environment?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the documentation clearly describe how to set up this environment and run through the self-test diagnostics?Using the provided documentation, setup the environment and run the tests. If the procedure is clear, answer YES, otherwise if the procedure requires you to contact the supplier in any manner or if there is no documentation, then enter NO.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5715DigitalAnalog/AMSI/O and ESDMemoryMEMSAre expected gate level discrepancies documented and explained?Considering the test environment, how clear are the test results? Is there documentation describing how to interpret the test results e.g. if terse results provided (such as a light blinking or a result number displayed) is there documentation regarding the meaning of such indications? If display strings or log files are used is there documentation describing the strings or messages?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5715DigitalAnalog/AMSMemoryMEMSAre test benches available from the vendor to test IP in the system?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSAre the test benches simulator-independent?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5718DigitalAnalog/AMSMemoryMEMSDo the IP test benches support mixed-signal simulation for mixed-signal circuitry?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10718DigitalAnalog/AMSMemoryMEMSDo the test benches cover 100% of the IP specification?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5718DigitalAnalog/AMSMemoryMEMSDo the test benches reflect the latest revisions to the specs?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10718Analog/AMSIs this IP a standard interface for a high-speed serial link protocol like PCI Express, USB or SATA?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Analog/AMSDupEnabledWas the IP tested in conjunction with a digital controller?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10723Analog/AMSDupEnabledIs there a documented methodology to measure Link Margin?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10723Analog/AMSDupEnabledIs a procedure outlined to examine the recovered Eye Diagram?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10723Analog/AMSDupEnabledIs any Receive Side Equalization available for improved link margin?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10723DigitalAnalog/AMSDoes the documented test methodology include testing asynchronous operation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSDoes the IP connect to an industry standard interface?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSDupEnabledDoes this Std interface require certification to be compliant?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0729DigitalAnalog/AMSDupEnabledHas this IP been certified?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10729DigitalAnalog/AMSDupEnabledWas the IP certified using test chips?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5729DigitalAnalog/AMSDupEnabledWas the IP certified by customers using this IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2729DigitalAnalog/AMSDupEnabledIs there a Compliance Certification Report available?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5729DigitalAnalog/AMSMemoryMEMSDoes the IP connect to chip pads (I/O pins)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryMEMSAre the IO cells/pads included in the IP deliverables?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0735DigitalAnalog/AMSMemoryMEMSAre ESD Protection Devices provided with the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryMEMSIs ESD data provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5737DigitalAnalog/AMSMemoryMEMSDupEnabledWhat is the HBM ESD Rating?Specify rating in comment block.IEEE P1734 QIP Working Group2008-04-19 00:00:00Optional0738DigitalAnalog/AMSMemoryMEMSDupEnabledWhat is the MM ESD Rating?Specify rating in comment block.IEEE P1734 QIP Working Group2008-04-19 00:00:00Optional0738DigitalAnalog/AMSMemoryMEMSDupEnabledWhat is the CDM ESD Rating?Specify rating in comment block.IEEE P1734 QIP Working Group2008-04-19 00:00:00Optional0738DigitalAnalog/AMSI/O and ESDMemoryMEMSIs ESD data available for all power supplies used by the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5737DigitalAnalog/AMSI/O and ESDMemoryMEMSIs the datecode of the model library clearly identified?The datecode provides further indication of the version/creation time and facilitates debug if any issues are encountered.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSAre all included I/O modeled?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryIs the power down leakage current specified?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryDupEnabledIs the quiescent supply current specified?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSIs there a link to the Foundry's web-site containing the process technology information (in which the IP is being implemented?) If so, please provide link in Comments section.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSI/O and ESDMemoryMEMSIs the IP designed to work across more than a single process option? (like G.LV,LVOD)IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSIs IP tagging done per each of the supported foundry specifications?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryMEMSDupEnabledHow many layers of metal does this IP require full use of?List in comment section.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryMEMSDupEnabledDoes the IP require partial use of a metal layer in addition to the full-use metal layers?Indicate partial use metal layer in the comment columnIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryMEMSDupEnabledDoes the IP require any thick metal layers?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryMEMSDupEnabledDoes the IP require any high resistance poly?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Analog/AMSMemoryMEMSIs this macro designed to interface with digital circuits?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Analog/AMSMemoryMEMSIs a digital placeholder model provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5754Analog/AMSMemoryMEMSIs a Functional / Timing Digital Simulation Model provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5754Analog/AMSMemoryMEMSIs a Digital Timing Model of the macro suitable for Static Timing Analysis provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5754Analog/AMSMemoryMEMSIs a peripheral interconnect model provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryIs the IP configurable?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalMemoryIs the IP designed to support instance by instance configurability?IP should ever be globally programmable.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5759DigitalAnalog/AMSCan you change the parametrics through pin programmability?Answer YES if the IP is configurable by either (i) pin programmability, (ii) block substitution, (iii) fuse programmability, or (iv) metal changesIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5759DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes the IP have a documented and well ordered directory structure?How straight forward is directory structure? How easy is it to incorporate component's directory structure with structure of product being developed? IP has a well organized directory structure. IP directories have a ReadMe file that explain the function of files in that directory. IP files follow some naming convention that makes it easy to understand the function of the files. An example is name_type.ext where type and ext are used to classify files. Example do_synth.cmd, sss_monitor.v, etc.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSWill the build environment automatically create any of the directories or intermediate working files it needs as part of the build process?Answer YES if, other than setting up the root directory, the build environment will automatically handle the creation of the sub-directory trees that it requires.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSMemoryMEMSHave module name-space collisions been avoided by adopting a non-interfering naming convention?Does the IP have a distinct prefix or suffix that helps to avoid name space collisions?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSExcept for the top-most level, are all file pathnames relative?You should answer NO to this question if the IP refers to absolute path names to a specific directory rather than relative pathnames to the root of the IP design tree.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSIs the IP independent of environment variables including the $PATH variable?Answer YES if the IP refers to files in the current directory as ./file_name instead of just file_name.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSAre the power and ground names in the analog domain named differently than the digital power & grounds?DO NOT Name Analog supply signals with the same names as the digital supply signals.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSIs IP designed with a building block approach with cleanly defined and functionally discrete sub-blocks?Answer YES if the IP can be updated to meet new requirements or a future update to the spec with modifications limited to as few internal sub-blocks as possible.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Analog/AMSMEMSHave Ideal elements and limitations of model been documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSI/O and ESDMemoryMEMSAre simulations being run over the appropriate combinations of case, voltage, and temperature?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSHave circuit performance characteristics been checked against datasheet requirements?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryMEMSAre test bench driver/monitors consistent with analog/mixed signal guidelines?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSHave circuits been simulated from full layout extraction with parasitic circuit elements, including thinox/poly/metal fill patterns?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSHave simulations been run with the most up to date device models?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryMEMSHave test points been added to circuits and any critical nodes?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSAre the ESD circuits derived from the standard cell library and/or approved by an ESD designer?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSAre the ESD protection circuits documented schematically, and verified against layout? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryMEMSIs documentation provided for snapback diodes needed between digital connections that cross vdd supplies (and the supplies are not diode connected)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSAll names consistent between all views, for example between circuit schematics and layout?This is a different question than the namespace issue, here, we're watching out for inconsistency naming between schematics and layout.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSAre effective ground senses routed through gnd busses where IR errors or IR noise injection could come into play? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSI/O and ESDMemoryMEMSIf the grounds should be routed in a separate ground route to the pad, are they routed in such a fashion? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSIf the reference circuit ground should be Kelvin sensed at the bandgap or initiating reference, is the ground configured as such?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSDo digital signals cross supply boundaries?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSAre level shifters used for all digital signals which cross supply boundaries?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10783DigitalAnalog/AMSMemoryMEMSAre power-ground pairs protected by diodes? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSAre multiple analog supplies diode protected between supplies (e.g. VDDA to GNDB)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSMEMSAre reference inputs filtered and sufficiently buffered?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSAre the signal polarities coming into and leaving the block as expected?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryDo critical signals need to be shielded? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryHave they been shielded?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10789Analog/AMSDo supplied bias currents match expected bias currents?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSFor remote ground sense lines, has the resistance been included in the simulation and evaluated?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSAre there latch-up and guard rings on devices connected to I/O, or is there at least 200 ohms in series with the output?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryHave loading conditions and I*R drops been evaluated for metal runners from subcircuits to pad?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSAre outputs/inputs from subcircuits wide enough?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSMEMSHave fill patterns for Thinox/Poly/Metal been placed so as to not compromise sensitive analog circuits?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSAre only Standard Devices required, i.e. no additional masks?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSHas a Product Brief (e.g. short 2-3 pg datasheet) been developed?Answer YES if the Product Brief has been developed and is available for customer use.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSI/O and ESDMemoryMEMSIs a Project Schedule available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSIs a system requirements document available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSIs a design specification document available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSAre design specification details cross referenced to the system requirements document?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSIs a process technology document available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSIs the technology defined in this document?All semiconductor processes which are compatible with the IP are described. These will include the process for which the IP was designed as well as any equivalent processes from other foundries.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10803DigitalAnalog/AMSI/O and ESDMemoryMEMSAre process tolerances described in this document?The process tolerances under which the IP specifications are met are described, including the effect of any process tuning.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10803DigitalAnalog/AMSI/O and ESDMemoryMEMSAre the sensitivity of the IP to process variation described in this document?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10803DigitalAnalog/AMSI/O and ESDMemoryMEMSIs a verification specification and detailed testplan document available?Answer YES if availableIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSAre verification specification details cross referenced to the system requirements document?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5807DigitalAnalog/AMSMemoryMEMSIs test coverage documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalMemoryFor IP containing digital circuits does the test fault coverage exceeds 98%?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5809Analog/AMSFor analog-only IP is the performance of all blocks verified?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5MemoryFor memory only IP are all support blocks fully tested, and are all normal operations (read / write / erase) tested at speed across worst-case data patterns?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSIs there a table of all tests and a description of each test in the test document, including a log of resources and time used?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSMemoryMEMSCan the DFT techniques run at speed?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSMemoryMEMSDoes the hard IP contain an automated test mode (IEEE 1149.4 boundary scan, scan chain, self-contained BIST, etc.)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSDo the automated test modes cover 100% of the hard IP circuitry (analog, digital, memory, etc.)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSIs there a IP specification that describes the models that will be included as part of the final deliverables - simulation, timing and floorplanning models?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSIs the library and version number used documented with the IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSIs the IP designed using a standard, documented methodology, adherence to which is reviewed and which can be examined by the IP integrator?As a minimum, the methodology should include regular intermediate steps and reviews during the design flow. Adherence to the methodology should be reviewed and documented with the IP. The methodology should be available for review by the integrator prior to design start. Assessment should be made of the thoroughness of the process as well as adherence to it.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryIs the architecture is readily adaptable to different but similar protocols?e.g. Adaptable from low speed to high speed (usb 1.1 to usb 2.0)IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Analog/AMSAre all digital outputs registered using digital standard cells?Exceptions should use other digital standard cells and be documentedIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSHave all analog output loads been documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSHas full buffering of clock and reset signals been provided in the analog IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSHave you assured that there is minimum load on the clock and reset inputs of the analog IP?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSIs the analog IP a PLL used for on-chip clock generation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Analog/AMSHas a method for bypassing the PLL been provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5825Analog/AMSIs a physical netlist for use in system level LVS provided?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSAre all matched transistors matched for direction of current flow?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10827Analog/AMSAre cascodes being driven off devices of the correct polarity? N channel cascode not driven by gate bias generated from a P channel deviceIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5827Analog/AMSAre matched devices of the same type? Poly resistor not matched to N tubIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10827Analog/AMSAre N channel current mirrors sinking current and P channel mirrors sourcing current?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSAre only top plates of capacitors tied to amplifier inputs?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSAre output-driving N channels GDNTR devices?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2Analog/AMSAre the structures which surround or overlay critically matched devices identical?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSDo the capacitors use minimum number of top and bottom plate contacts, unless more are required for circuit performance?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSAre all amplifier power and ground taps single-point taps? especially if the circuits have significant gain or are powered from rails that could have significant IR drop in them.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSIs a full circuit level netlist provided for simulation?This should include parasitics and be accompanied by all information that is required to enable simulation of the IPIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSHave all circuits been checked for valid power down?Power-down mode helps to find phantom dc currents, even if power-down is not a chip requirement.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSHas the pulsed stability on elements in feedback been checked?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSHas the stability for all elements in feedback loops been checked?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSHas the startup conditions for output glitches coming out of power down been checked?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSHas the gate poly connections been verified to have no dc current flow?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSHas the resistance of needed gate connections to large devices, and added metal route and contacts been checked? High gate resistance can create tau's that eat into phase margin and/or settling time.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSDo all circuits power down completely? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSIs there no excessive or transient leakage during powerdown on active power-down devices on all bias nodes?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSDo runners and contacts meet electromigration rules?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSAre all specifications measured and compliant?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSHas a ramp of the supply been run? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSHas a supply step been simulated? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSHave DC match simulations been run to check offset?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSHave dummy devices been placed around matched devices?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSHave extra devices been laid in where possible in a manner to allow changes at metal?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSIs double buffering (2 inverters) for all digital inputs needed? IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Analog/AMSIf digital signals are not re-buffered on the analog supply, has PSRR of the analog circuits been simulated?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10853Analog/AMSIs the edge of the Ntub pulled back far enough next to devices that need good/critical matching?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSI/O and ESDMemoryMEMSAre schematics easy to read (see comments)?Answer YES if you have asked another designer to review your schematics and they found the schematics easy to read, avoidance of rat's nest of wires, with power flows from top to bottom, signal flows left to right, as minimal use of connections via wire labels.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSI/O and ESDMemoryMEMSAre design schematics commented to describe circuit operation, power flow and a brief revision history?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2Analog/AMSI/O and ESDMemoryMEMSDo design schematics contain special instructions required for physical implementation of the circuit?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2DigitalAnalog/AMSI/O and ESDMemoryMEMSAre all inputs protected from antenna faults?Exceptions must be documentedIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSWas power analysis performed using extracted data to determine that the physical design meets power goals, including IR drop requirements of the design and electromigration rules of the process?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSIs a single library, or a consistent set of libraries used throughout the whole design?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSDoes the design require embedded memories?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSCan the design accommodate a variety of memory suppliers?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5862DigitalAnalog/AMSIs the memory interface parametric in size?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2862DigitalMemoryHas the static timing been run with signal integrity and cross talk effects?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSMemoryMEMSHas the design been run with on-chip-variation or included additional setup and hold margins?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSIs the timing verified for setup and hold at worst case and best case corners?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryMEMSIs the timing verified with best case and worst case RC extraction?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSIs device matching required in the design?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0Analog/AMSAre all devices that must match at the same orientation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5869DigitalAnalog/AMSAre device width and number of gate fingers LVS matched?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryDoes the IP contain digital standard cells that are pre-placed & routed?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryHas the standard cell library been verified in silicon?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5872DigitalAnalog/AMSMemoryHas the standard cell library performance been verified across voltage, process and temperature?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10872DigitalAnalog/AMSMemoryAre prefixes used to avoid cell name collisions in the standard cells?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5872DigitalAnalog/AMSMemoryIs the timing data provided across all process variation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5872DigitalAnalog/AMSDo post-layout simulations using layout parasitic extraction values for resistance and capacitance pass for all critical circuits?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSHave electromigration rules been checked against layout for all nets in the layout?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSAre general naming standards followed?Documented naming conventions used consistently throughout the design. Names used in RTL match names used in design documentation, and these are short and meaningful. Lowercase letters for all signal names, variable names, and port names. Uppercase letters for names of constants and user-defined types. Characters used only from the set [a-z,A-Z,0-9,_] in all names; all names begin with a letter. Maximum name size is 32 characters and minimum name size is 3 characters. Names are not reused for different classes of identifier, and do not use case to differentiate identifiers (e.g. clk vs. Clk)IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2DigitalAnalog/AMSMemoryMEMSAre specific signal naming standards adhered to and documented?Clock signals are readily identifiable - e.g. using prefix "clk" All clocks with the same name throughout the hierarchy should come from the same source. Scan signals are readily identifiable - e.g. using prefix "scan" Reset signals are readily identifiable - e.g. using prefix "rst" Process labels are readily identifiable - e.g. suffix "_PROC" Instance labels are readily identifiable - e.g. prefix "u_". They also bear the name of the module with a numeric suffix to differentiate. Indication of active-low signals should be consistent through-out the design, and the standard used should be given in the user documentation.IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nGuideline2DigitalAnalog/AMSI/O and ESDMemoryMEMSDo all files containing scripting language code (e.g. Perl, AWK, SED, Synthesis, Scan insertion, etc) begin with a comment block describing the file, its purpose, and its revision history?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSDoes each executable script contain a "-h" or help switch that explains its use?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSAre all hard-coded numbers, data values, or filenames represented by variables set at the top of the script?IEEE P1734 QIP Working Group2008-04-19 00:00:00a/o/nRule5DigitalAnalog/AMSMemoryDoes the IP incorporate BIST?BIST procedures should be implemented in IPs where they would significantly improve the testability of the IP analog and digital sectionsIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nOptional0DigitalAnalog/AMSMemoryHave all BIST requirements have been addressed and documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5884Analog/AMSHas a test method been provided for the analog circuitry?This should take the form of a fully characterized and described procedure where this will not seriously impact the analog behavior of the circuit. As many critical analog circuits and nodes should be testable as possibleIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSDoes the IP contain a IEEE 1149.4 analog boundary scan implementation?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5886Analog/AMSDoes the analog circuitry implement have a "sleep" state that permits digital IDDQ testingIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10886Analog/AMSHave test Isolation requirements been addressed and documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSIs LVS clean flat (no hierarchy) with 0% parameter tolerance?Known errors and waivers are documented or listed in comment field.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSIs LVS clean hierarchically with 0% parameter tolerance?Known errors and waivers are documented or listed in comment field.IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSAre DRC, ERC and antenna clean flat (no hierarchy and no errors)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSIs DRC, ERC and antenna clean hierarchically with 0% parameter tolerance?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSDo the cell names match?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSDo the pin names match?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSDo the power and ground pins match?This may not be relevant for timing views, but in some cases, reference voltage pins are included in timing views)IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSDo the pin directions match between verilog and the timing library model and the SPICE level netlist?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryMEMSDo the timing arcs match between the verilog model and the timing library file?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryMEMSDoes the timing arc sense match between the verilog and timing model?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryMEMSDo the timing arc types match between the verilog and timing model?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSHave start-up and operating conditions been checked to avoid balanced differential common-mode latch-up. ?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSHave you verified that matched transistors under metal is not problematic?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSHave you verified that the power and ground busing within the IP can handle the peak current requirements at maximum frequency?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSI/O and ESDMemoryMEMSAre all test modes of the IP described including how to access them, specific instructions on their use and what tests can be run in each mode?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSMEMSAre methods provided for testing or directly accessing the analog circuitry in the IP including the signals and controls available, access registers and how to make measurements and use the results?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSI/O and ESDMemoryMEMSAre details of all characterization tests to be carried out on the IP described, including required external circuitry, estimated times to complete the tests and any assumptions made about the test environment?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSAfter physical implementation of the IP were all necessary functional and parametric performances simulated, including the effects of parasitic capacitance and resistance?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSAre all IP specifications which cannot be guaranteed by the described tests explicitly labeled?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryMEMSIs the full IP simulated with digital and analog transistor netlists?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2DigitalAnalog/AMSMemoryMEMSHas the transistor mismatch data been verified with Monte Carlo simulations?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSIs the IP Characterized for noise sensitivity?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10Analog/AMSIs a noise report available?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5911Analog/AMSAre floorplan noise considerations documented? Assessment of noise source/noise tolerance for sensitive IPIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5911Analog/AMSDoes noise isolation that requires any special packaging constraints documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5911Analog/AMSAre noise isolation special packaging constraints documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5911Analog/AMSAre the device model date codes and revision information documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSAre the effects of well proximity simulated in the design?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSAre STI stress effects simulated in the design?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSHas hot carrier degradation been simulated for critical analog circuits?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSHas NBTI Vt shifts been simulated in PMOS circuits?Different Vgs voltages for extended periods of time will shift VtIEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSHave simulations with output and input buffers and also package parasitics been run on output and input blocks?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5MEMSHas the design been analyzed for safety issues due to component failures? (e.g. combustible components)IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nImperative10DigitalAnalog/AMSMemoryIs the default configuration of Verification Environment well-documented?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryDoes the simulation script detect simulator errors and warnings?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryIs every single regression test able to run stand-alone?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryDoes the regression environment support running the regression suite with a single submission?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryCan the regression be batched off to computer farm on the networks?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalAnalog/AMSMemoryDoes the log file contain all information needed to reproduce the run?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5Analog/AMSIf AMS, have split lots for design elements, for example transistors and resistors, been characterized?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalHas latch-up been tested?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5DigitalDid the latch-up testing conform to the appropriate industry standards (list standards in comments)?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nRule5930DigitalAnalog/AMSMemoryMEMSHas the IP been tested for reliability under external shorts?IEEE P1734 QIP Working Group2008-04-19 00:00:00y/nGuideline2