ATML-TD-Ex1 file://D:/Work/ATML/TestDescription/Samples/TheoryOfOperationSample.doc /TestDescription/UUT/TestData/PowerRequirements/DCPowerRequirements/DCPowerRequirement[@ID="1"]/Connection/Ports/Port[@name="HI"] /TestDescription/InterfaceRequirements/c:Ports/c:Port[@name="P1"]/c:ConnectorPins/c:ConnectorPin[@connectorID="J1" and @pinID="1"] /TestDescription/UUT/TestData/PowerRequirements/DCPowerRequirements/DCPowerRequirement[@ID="1"]/Connection/Ports/Port[@name="LO"] /TestDescription/InterfaceRequirements/c:Ports/c:Port[@name="P1"]/c:ConnectorPins/c:ConnectorPin[@connectorID="J1" and @pinID="2"] /TestDescription/UUT/TestData/PowerRequirements/ACPowerRequirements/ACPowerRequirement[@ID="1"]/Connection/Ports/Port[@name="HI"] /TestDescription/InterfaceRequirements/c:Ports/c:Port[@name="P1"]/c:ConnectorPins/c:ConnectorPin[@connectorID="J1" and @pinID="3"] /TestDescription/UUT/TestData/PowerRequirements/ACPowerRequirements/ACPowerRequirement[@ID="1"]/Connection/Ports/Port[@name="LO"] /TestDescription/InterfaceRequirements/c:Ports/c:Port[@name="P1"]/c:ConnectorPins/c:ConnectorPin[@connectorID="J1" and @pinID="4"] V_I Input Input signal GND Bi-Directional Ground connection for Input signal V_O Output Output signal GND Bi-Directional Ground connection for Output signal V_CC Input DC Power GND Bi-Directional Ground connection for DC Power EX1-C1 Apply power to UUT With power off, measure resistance between V_CC and GND. With power on, measure DC voltage at the output With power on and input signal present, measure AC voltage at the output. With power on and input signal present, probe AC voltage at the collector of Q1 With power on, probe DC voltage at the collector of Q1 With power on, probe DC voltage at the emitter of Q1 With power on, probe DC voltage at the base of Q1 file://D:/Work/ATML/TestDescription/Samples/SampleDiagnosticModel.xml Resistor Open Resistor Open Resistor Open Resistor Open Capacitor Open Short Capacitor Open Short Capacitor Open Short Transistor dummy Short /TestDescription/FailureFaultData/FaultData/Components/Component[@ID="c8"]/Interface/c:Ports/c:Port/c:ConnectorPins/c:ConnectorPin[@connectorID="c1" and @pinID="B"] /TestDescription/FailureFaultData/FaultData/Components/Component[@ID="c8"]/Interface/c:Ports/c:Port/c:ConnectorPins/c:ConnectorPin[@connectorID="c1" and @pinID="E"] Open /TestDescription/FailureFaultData/FaultData/Components/Component[@ID="c8"]/Interface/c:Ports/c:Port/c:ConnectorPins/c:ConnectorPin[@connectorID="c1" and @pinID="B"] Short /TestDescription/FailureFaultData/FaultData/Components/Component[@ID="c8"]/Interface/c:Ports/c:Port/c:ConnectorPins/c:ConnectorPin[@connectorID="c1" and @pinID="C"] /TestDescription/FailureFaultData/FaultData/Components/Component[@ID="c8"]/Interface/c:Ports/c:Port/c:ConnectorPins/c:ConnectorPin[@connectorID="c1" and @pinID="E"] Open /TestDescription/FailureFaultData/FaultData/Components/Component[@ID="c8"]/Interface/c:Ports/c:Port/c:ConnectorPins/c:ConnectorPin[@connectorID="c1" and @pinID="C"] Short /TestDescription/FailureFaultData/FaultData/Components/Component[@ID="c8"]/Interface/c:Ports/c:Port/c:ConnectorPins/c:ConnectorPin[@connectorID="c1" and @pinID="B"] /TestDescription/FailureFaultData/FaultData/Components/Component[@ID="c8"]/Interface/c:Ports/c:Port/c:ConnectorPins/c:ConnectorPin[@connectorID="c1" and @pinID="C"] Open /TestDescription/FailureFaultData/FaultData/Components/Component[@ID="c8"]/Interface/c:Ports/c:Port/c:ConnectorPins/c:ConnectorPin[@connectorID="c1" and @pinID="E"]