The IEEE P1641 default Test Signal Framework Library for certain digital Signals This XML instance file is specified in IEEE Std 1641-20XX, "IEEE Standard for Signal and Test Definition." This schema is a World Wide Web Consortium (W3C) Extensible Markup Language (XML) binding of Annex L Test Signal Framework (TSF) for Digital Pulse Classes TSF library definition in XML" The purpose of this XML file is to provide unique TSF definitions inline with legacy ATLAS 716 signals.This files uses the W3C XML Schema definition language as the encoding. This allows for interoperability and the exchange of TSF component instances between various systems.This file shall not be modified but may be included in derivative works. Copyright (c) 2009 Institute of Electrical and Electronics Engineers, Inc. USE AT YOUR OWN RISK The Pulse Classes Family of TSFs: The Pulse Classes TSFs are designed to be used with an event stream instead of the other digital TSFs or BSCs. A simple HL data stream could be created, for illustrative purposes, using a Clock event to generate the data. The intention however, is to use Encode to generate the data and for the Pulse Class to turn it into a real signal. Similarly, Decode is available to allow incoming digital signals to be measured and compared to the expected values. The DTIF TSF: The DTIF TSF represents the simplest TSF and contains only the 'location' of the DTIF files and a definition of how they will be used, allowing for the generation of a complete digital stream containing all the patterns and necessary timing sets such that the output from the DTIF TSF represents the complete digital pattern for all channels. The method of using a DTIF TSF would be to: * add a Pulse Class to convert digital stream into correct logic levels * add a Digital Pins connector to identify the UUT pins for the signals. Pulse Class to condition a digital stream to a Basic Non Return-to-Zero physical output. A pulse class in which the digital data is carried by two physical signal levels (most often two voltage levels), in which one level represents a logic one or High and the other represents a logic zero or Low. The amplitude of the Logic High in voltage or current. The amplitude of the Logic Low in voltage or current. Pulse Class to condition a digital stream to a Basic Return-to-Zero physical output. A pulse class in which each bit period is subdivided into two sub-periods. The binary data is carried in the first sub-period. A logic one or High is carried by a pulse of one amplitude and the logic zero or Low is carried by a pulse of a different amplitude. The second sub-period contains a "no pulse" condition, which is at the same level as the logic zero amplitude. The amplitude of the Logic High in voltage or current. The amplitude of the Logic Low in voltage or current. Input for the digital clock. This is a signal input and does not require a value. Pulse Class to condition a digital stream to a Bi-Phase Level physical output. A pulse class in which each bit period is subdivided into two sub-periods. The binary data is carried by the transition of the signal level during each bit period, i.e. the amplitude is at one level during the first sub-period and at another level during the second sub-period. A logic one or High is carried by two sub-periods in which the first is at the high amplitude level and the second sub-period is at the low (zero) amplitude. A logic zero or Low is carried by two sub-periods in which the first is at the low (zero) amplitude level and the second sub-period is at the high amplitude. The amplitude of the Logic High in voltage or current. The amplitude of the Logic Low in voltage or current. Input for the digital clock. This is a signal input and does not require a value. Pulse Class to condition a digital stream to a Bi-Phase Space physical output. A pulse class in which each bit period is subdivided into two sub-periods. A transition occurs at the start of each full bit period. The logic one or High is represented by a second transition at the start of the second sub-period. The logic zero or Low has no second transition and the level remains unchanged for the whole period. The amplitude of the Logic High in voltage or current. The amplitude of the Logic Low in voltage or current. Input for the digital clock. This is a signal input and does not require a value. Input for the doubled digital clock. This is a signal input and does not require a value. Pulse Class to condition a digital stream to a Bi-Phase Mark physical output. A pulse class in which each bit period is subdivided into two sub-periods. A transition occurs at the start of each full bit period. The logic zero or Low is represented by a second transition at the start of the second sub-period. The logic one or High has no second transition and the level remains unchanged for the whole period. The amplitude of the Logic High in voltage or current. The amplitude of the Logic Low in voltage or current. Input for the digital clock. This is a signal input and does not require a value. Input for the doubled digital clock. This is a signal input and does not require a value. PPulse Class to condition a digital stream to a Return-to-Zero Bipolar physical output. A pulse class in which each bit period is subdivided into two sub-periods. Three signal levels are used and each bit is represented by the level during the first sub-period. The logic one or High is represented by the first sub period at a specified amplitude followed by the second sub-period at zero amplitude. The logic zero or Low is represented by the first sub period at second (normally negative) amplitude followed by the second sub-period at zero amplitude. The amplitude of the Logic High in voltage or current. The amplitude of the Logic Low in voltage or current. Input for the digital clock. This is a signal input and does not require a value. Pulse Class to condition a digital stream to a Return-to-Zero Pulse physical output. This pulse class is very similar to BasicRZ, but with a duty cycle of 25 percent. The amplitude of the Logic High in voltage or current. The amplitude of the Logic Low in voltage or current. Input for the digital clock. This is a signal input and does not require a value. Input for the doubled digital clock. This is a signal input and does not require a value. Pulse Class to condition a digital stream to an Alternate Mark Inversion physical output. The alternate mark inversion (AMI) pulse class requires three amplitude levels need to be defined. In this TSF only two of the amplitudes are specified as the inverted logic one or High level is assumed to be of the same amplitude as the non-inverted logic one or High but with the opposite sign. The logic one amplitudes are offset from the amplitude specified for the logic zero or Low. The amplitude of the Logic High in voltage or current. The amplitude of the Logic Low in voltage or current. Input for the digital clock. This is a signal input and does not require a value. The DTIF TSF represents a simple TSF and contains only the 'location' of the DTIF files and a definition of how they will be used. This TSF allows for the generation of a complete digital signal stream containing all the digital patterns and necessary timing information. This TSF provides support for digital data files defined in IEEE Std 1445™–1998, IEEE Standard for Digital Test Interchange Format. The path to the directory containing the DTIF files. Type of test run to be performed.