Working Group Icon

Computer Technology Working Groups

Displaying results 1 - 40 of 99
Working Group Name
StatusHelp
Cloud Profiles WG (CPWG) Working Group This guide advises cloud computing ecosystem participants (cloud vendors, service providers, and users) of standards-based choices in areas such... Active Working Group
Intercloud WG (ICWG) Working Group This standard defines topology, functions, and governance for cloud-to-cloud interoperability and federation. Topological elements include clouds,... Active Working Group
Property Specification Language Working Group The Accellera Property Specification Language (PSL), a language for formal specification of electronic system behavior, was developed by Accellera... Active Working Group
Advanced Library Format Working Group Define and release a standard specification for modeling next-generation silicon including timing, power, signal integrity, synthesis, test, and... Active Working Group
Working Group for Design Intellectual Property (IP) Encryption and Rights Management The intent of this document is to enable design flows that provide interoperability between IP sources, tools, integrators, and users of the IP.... Active Working Group
C/DA/IPXACT IP-XACT Standardization Working Group Conformance checks for eXtensible Markup Language (XML) data designed to describe electronic systems are formulated by this standard. The meta... Active Working Group
mat for LSI-Package-Board Interoperable Design This standard defines a common interoperable format used for the design of (a) Large Scale Integrated (LSI) circuits, (b) Packages for such LSI... Active Working Group
Open Model Forum Working Group To provide a standard method for interfacing and managing complex electronic models to design automation tools. This method is aimed at providing... Active Working Group
VHDL Analysis and Standardization Group VASG is responsible for maintaining and extending the VHDL standard (IEEE 1076). Current News: 1076-2008 was approved by REVCOM in September 2008.... Active Working Group
Rosetta Systems Level Design Language Working Group System-level design is characterized by the need to integrate information from many heterogeneous domains when making engineering decisions. Thus,... Active Working Group
VHDL Register Transfer Level (RTL) Synthesis Working Group This document specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable... Active Working Group
SPIRIT Standardization Working Group The purpose of this project is to provide a well-defined XML Schema for meta-data that documents the characteristics of Intellectual Property (IP)... Active Working Group
Standards Packages Working Group The Working Group will define a collection of VHDL Std 1076.1 packages compatible with IEEE Std. 1076.1-1999, along with recommendations for... Active Working Group
Power Modeling: Enabling System Level Analysis This standard proposes a meta-model / meta-standard focused on parameterization and abstraction, enabling system, software and hardware IP-centric... Active Working Group
System C Standardization Working Group The general charter of this project is to provide a C++-based standard for designers and architects who need to address complex systems that are a... Active Working Group
UHA: Unified Hardware Abstraction and Layer The new standard defines the syntax and semantics for energy oriented description of hardware, software and power management for electronic... Active Working Group
Working Group for VHDL Multiple Energy Domain Support The Working Group will define a collection of VHDL Std 1076.1 packages compatible with IEEE Std. 1076.1-1999, along with recommendations for... Active Working Group
VITAL Application Specific Integrated Circuit Working Group The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a... Active Working Group
Verilog Register Transfer Level Synthesis Working Group To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is... Active Working Group
VHDL Language Working Group VASG is responsible for maintaining and extending the VHDL standard (IEEE 1076). Current News: 1076-2008 was approved by REVCOM in September 2008.... Active Working Group
Verilog Hardware Description Language Working Group The Insititue of Electrical and Electronics Engineers (IEEE) (website) Standards Group for Verilog, known colloquially as the "e;VSG"e;,... Active Working Group
Integrated Circuit (IC) Open Library Architecture (OLA) Working Group The IEEE1481 Reflector Archives contain workgroup Minutes and shared documents for the workgroup. The archives dates from 2002 to the present. The... Active Working Group
Functional Verification Language e Working Group The e functional verification language is an application-specific programming language, aimed at automating the task of verifying a hardware or... Active Working Group
Design Process Documentation and Fragmentation The goal of this specification is twofold. First it provides method designers with a template for describing their own method fragments. Every... Active Working Group
Working Group for 1667 he IEEE 1667 protocol defines a standard protocol for secure authentication and creation of trust between a secure host and a directly attached... Active Working Group
Displaying results 1 - 40 of 99 - all