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Standards Development Working Group

VLOGSyn - Verilog Register Transfer Level Synthesis Working Group

To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing IEEE 1364 standard.

  • Status: Active Standard Help

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