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JTAG - Compact JTAG Working Group

This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip test access ports (TAPs) specified by IEEE Std 1149.1-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 test access ports (TAP.7s), T0 - T5, with each class providing incremental capability, building upon that of the lower-level classes. Class T0 provides the behavior specified by 1149.1 from start-up when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system
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