Boundary Scan Architecture - Standard Test Access and Boundary Scan Architecture WG P1149.1

The IEEE 1149.1 standard defines test logic that can be included in an integrated circuit to provide standardized approaches to — testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate; — testing the integrated circuit itself; and — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).