A language to describes test constructs such as test patterns, different configurations of a design etc. is defined to allow for reuse test methodologies in a System on a Chip flow. The language is commonly known as CTL (Core Test Language). This standard provides the necessary language constructs that are needed for the IEEE 1500 standard. CTL is used in the industry in hierarchical flows to alleviate the capacity problems when dealing with Design For Test (DFT) synthesis. CTL can be used as a language to provide all the design configuration for chips being tested to feed into an ATE (Tester) environment. A part of CTL includes the definition of reusable test patterns for a design hierarchy. For this portion the STIL standard is leveraged, thus CTL patterns represent restricted STIL test patterns.
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