The purpose of the standard is to perform the following: - Establish a common framework of the V&V processes, activities, and tasks in support of all system, software, and hardware life cycle processes - Define the V&V tasks, required inputs, and required outputs in each life cycle process The purpose of the standard is to perform the following: - Establish a common framework of the V&V processes, activities, and tasks in support of all system, software, and hardware life cycle processes - Define the V&V tasks, required inputs, and required outputs in each life cycle processThis verification and validation (V&V) standard is a process standard that addresses all system and software life cycle processes including the Agreement, Organizational Project-Enabling, Project, Technical, Software Implementation, Software Support, and Software Reuse process groups. This standard is compatible with all life cycle models (e.g., system, software, and hardware); however, not all life cycle models use all of the processes listed in this standard. V&V processes determine whether the development products of a given activity conform to the requirements of that activity and whether the product satisfies its intended use and user needs. This determination may include the analysis, evaluation, review, inspection, assessment, and testing of products and processes. The user of this standard may invoke those life cycle processes and the associated V&V processes that apply to the project. A description of system life cycle processes may be found in ISO/IEC 15288:2008, and a description of software life cycle processes may be found in ISO/IEC 12207:2008 and IEEE Std 1074TM-2006. Annex A maps ISO/IEC 15288:2008(E) (Table A.1 and Table A.2) and ISO/IEC 12207:2008 (Table A.3 and Table A.4) to the V&V activities and tasks defined in this standard. This standard defines the verification and validation processes that are applied to the system, software, and hardware development throughout the life cycle, including acquisition, supply, development, operations, maintenance, and retirement. This standard applies to the system, software, and hardware being acquired, developed, maintained, or reused. The term software also includes firmware and microcode (e.g., Field Programmable Gate Arrays and Programmable Logic Devices). Each of the terms system, software, and hardware includes its associated documentation. V&V processes consist of the Verification Process and Validation Process. The Verification Process provides objective evidence for whether the products perform the following: a) Conform to requirements (e.g., for correctness, completeness, consistency, and accuracy) for all activities during each life cycle process b) Satisfy the standards, practices, and conventions during life cycle processes c) Successfully complete each life cycle activity and satisfy all the criteria for initiating succeeding life cycle activities (i.e., builds the product correctly) The Validation Process provides evidence for whether the products perform the following: - Satisfy system requirements allocated to the products at the end of each life cycle activity - Solve the right problem (e.g., correctly model physical laws, implement business rules, and use the proper system assumptions) - Satisfy intended use and user needs in the operational environment (i.e., builds the correct product) The Verification Process and the Validation Process are interrelated and complementary processes that use each other's process results to establish better completion criteria and analysis, evaluation, review, inspection, assessment, and test V&V tasks for each life cycle activity. The V&V task criteria described in Table 1a through Table 1d explicitly define the conformance requirements for V&V processes. The development of a sufficient body of evidence requires a trade-off between the amount of time spent and a finite set of system conditions and assumptions against which to perform the V&V tasks. Each project should define criteria for a sufficient body of evidence (i.e., selecting an integrity level establishes one of the basic parameters), time schedule, and scope of the V&V analysis and test tasks (i.e., range of system conditions and assumptions). This standard does not assign the responsibility for performing the V&V tasks to any specific organization. The analysis, evaluation, and test activities may be performed by multiple organizations; however, the methods and purpose will differ for each organization's functional objectives. ISO/IEC 15288:2008 and ISO/IEC 12207:2008 require that the developer perform various testing and evaluation tasks as an integral part of implementation. The techniques described in this standard may be useful in performing the developer's tests and evaluations. Therefore, whenever this standard mentions the developer's performance of a verification or validation activity, it is to be understood that the reference applies to the test and evaluation tasks of implementation.
Working Group: 1012_WG - Std for Software Verification and Validation Working Group
Sponsor: C/S2ESC - Software & Systems Engineering Standards Committee
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